X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FCANBT.h;h=7029dbddef2c48aa294d3cbdf0cbeadcad63db08;hb=258c37b147353bc522ffc33dfbd7d0d9cd7c32d7;hp=ae32f6b14acd393b21569e54a9b378335de04c1a;hpb=2c4faea84f3d96d674e3c065e1f220b20c8930c0;p=u-boot

diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h
index ae32f6b14a..7029dbddef 100644
--- a/include/configs/CANBT.h
+++ b/include/configs/CANBT.h
@@ -181,15 +181,6 @@
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
 /*
  * Init Memory Controller:
  *