X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FCPCI405.h;h=9c0412932a0573f042b802bab82cc6dc75a687a3;hb=0f92c7e7c9a62755b1457d3c46f93c8c1f6c19fc;hp=047e2f1eef9cc57f7a5ba6517de8cf828d2f358b;hpb=7b230f61db319d87d51449d4620d520822813fbb;p=u-boot

diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index 047e2f1eef..9c0412932a 100644
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -55,6 +55,10 @@
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI	1
+#undef  CONFIG_HAS_ETH1
 
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
 				 CONFIG_BOOTP_DNS | \
@@ -79,8 +83,6 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
-#define CFG_NAND_LEGACY
-
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/