X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FCPCI405AB.h;h=9122cbd8779ec5a27020b1a44b6c9c3d55d6c193;hb=1c1b7c3739095da7d73fef3adbe9f187791ca9ff;hp=41795a7726462d95e6fbd23b7e1794c37092fc92;hpb=ee1702d75a30d076139d1841383a1fa7220a0e11;p=u-boot

diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index 41795a7726..9122cbd877 100644
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -39,7 +39,10 @@
 #define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
 #define CONFIG_CPCI405AB	1	/* ...and special AB version	*/
 
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	 1	/* call misc_init_r()		*/
 
 #define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
 
@@ -60,7 +63,6 @@
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
 
-#define CONFIG_NET_MULTI	1
 #undef  CONFIG_HAS_ETH1
 
 #define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
@@ -112,9 +114,6 @@
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-#endif
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
@@ -132,6 +131,12 @@
 #define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
 #undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
 #define CONFIG_SYS_BASE_BAUD	    691200
 
@@ -187,7 +192,9 @@
 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
 #define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
 #define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
+
+#define CONFIG_PCI_4xx_PTM_OVERWRITE	1 /* overwrite PTMx settings by env */
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
@@ -256,6 +263,7 @@
  * I2C EEPROM (CAT24WC32) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
@@ -376,18 +384,8 @@
 #define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
 
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
 #endif	/* __CONFIG_H */