X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FCPCI405DT.h;h=9b99ba8664f3ed241e900b30b46dcdb179fe731b;hb=7b89795f17c990263a17ecf25e447df16e379748;hp=07acab0c2b6e20f051b7716858e945e16a774270;hpb=83653121d7382fccfe329cb732f77f116341ef1d;p=u-boot diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 07acab0c2b..9b99ba8664 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -38,6 +38,8 @@ #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ +#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 + #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ @@ -135,6 +137,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 @@ -383,17 +391,8 @@ #define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - #endif /* __CONFIG_H */