X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FCPCI750.h;h=d516c3cb8128e0f11faeb0ba7919ef7b7bcabf30;hb=06015146a15adc7455440c491d543f6a8091551d;hp=150e5267f21ae0a0bb37b630e0bf307b3388aaca;hpb=a7b9fb9110e3c0be644b3e2c8f397f606138a710;p=u-boot diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 150e5267f2..d516c3cb81 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -57,46 +57,49 @@ #define CONFIG_CPCI750 1 /* this is an CPCI750 board */ -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */ +#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */ #undef CONFIG_ECC /* enable ECC support */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* which initialization functions to call for this board */ #define CONFIG_MISC_INIT_R #define CONFIG_BOARD_PRE_INIT #define CONFIG_BOARD_EARLY_INIT_F 1 -#define CFG_BOARD_NAME "CPCI750" +#define CONFIG_SYS_BOARD_NAME "CPCI750" #define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX" -/*#define CFG_HUSH_PARSER*/ -#define CFG_HUSH_PARSER +/*#define CONFIG_SYS_HUSH_PARSER*/ +#define CONFIG_SYS_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CFG_AUTO_COMPLETE 1 +#define CONFIG_CMDLINE_EDITING /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ /* Define which ETH port will be used for connecting the network */ -#define CFG_ETH_PORT ETH_0 +#define CONFIG_SYS_ETH_PORT ETH_0 /* * The following defines let you select what serial you want to use * for your console driver. * * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CFG_DUART port from 1 + * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial + * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 * to 0 below. * * to use the MPSC, #define CONFIG_MPSC. If you have wired up another * mpsc channel, change CONFIG_MPSC_PORT to the desired value. */ -#define CONFIG_MPSC +#define CONFIG_MPSC #define CONFIG_MPSC_PORT 0 /* to change the default ethernet port, use this define (options: 0, 1, 2) */ #define CONFIG_NET_MULTI -#define MV_ETH_DEVS 1 +#define MV_ETH_DEVS 1 #define CONFIG_ETHER_PORT 0 #undef CONFIG_ETHER_PORT_MII /* use RMII */ @@ -118,123 +121,130 @@ #define CONFIG_SERIAL "AA000001" #define CONFIG_SERVERIP "10.0.0.79" -#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s" +#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s" #define CONFIG_TESTDRAMDATA y -#define CONFIG_TESTDRAMADDRESS n +#define CONFIG_TESTDRAMADDRESS n #define CONFIG_TESETDRAMWALK n /* ----------------------------------------------------------------------------- */ -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) - - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_I2C \ - | CFG_CMD_CACHE \ - | CFG_CMD_EEPROM \ - | CFG_CMD_PCI \ - | CFG_CMD_ELF \ - | CFG_CMD_DATE \ - | CFG_CMD_NET \ - | CFG_CMD_PING \ - | CFG_CMD_IDE \ - | CFG_CMD_FAT \ - | CFG_CMD_EXT2 \ - ) +#undef CONFIG_ALTIVEC /* undef to disable */ -#define CONFIG_DOS_PARTITION +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_PCI +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + + +#define CONFIG_DOS_PARTITION #define CONFIG_USE_CPCIDVI -#ifdef CONFIG_USE_CPCIDVI +#ifdef CONFIG_USE_CPCIDVI #define CONFIG_VIDEO #define CONFIG_VIDEO_CT69000 #define CONFIG_CFB_CONSOLE #define CONFIG_VIDEO_SW_CURSOR #define CONFIG_VIDEO_LOGO #define CONFIG_I8042_KBD -#define CFG_ISA_IO 0 +#define CONFIG_SYS_ISA_IO 0 #endif /* * Miscellaneous configurable options */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_SPEED 80000 /* I2C speed default */ - -#define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed default */ + +#define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -/*#define CFG_MEMTEST_START 0x00400000*/ /* memtest works on */ -/*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ -/*#define CFG_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */ +/*#define CONFIG_SYS_MEMTEST_START 0x00400000*/ /* memtest works on */ +/*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ +/*#define CONFIG_SYS_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */ /* -#define CFG_DRAM_TEST +#define CONFIG_SYS_DRAM_TEST * DRAM tests - * CFG_DRAM_TEST - enables the following tests. + * CONFIG_SYS_DRAM_TEST - enables the following tests. * - * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. + * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines + * Environment variable 'test_dram_data' must be + * set to 'y'. + * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely + * addressable. Environment variable + * 'test_dram_address' must be set to 'y'. + * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. + * This test takes about 6 minutes to test 64 MB. + * Environment variable 'test_dram_walk' must be + * set to 'y'. */ -#define CFG_DRAM_TEST -#if defined(CFG_DRAM_TEST) -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -/*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ -#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ -#define CFG_DRAM_TEST_DATA -#define CFG_DRAM_TEST_ADDRESS -#define CFG_DRAM_TEST_WALK -#endif /* CFG_DRAM_TEST */ +#define CONFIG_SYS_DRAM_TEST +#if defined(CONFIG_SYS_DRAM_TEST) +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ +/*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ +#define CONFIG_SYS_DRAM_TEST_DATA +#define CONFIG_SYS_DRAM_TEST_ADDRESS +#define CONFIG_SYS_DRAM_TEST_WALK +#endif /* CONFIG_SYS_DRAM_TEST */ #define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ -#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ +#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ -#define CFG_LOAD_ADDR 0x00300000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ -#define CFG_HZ 1000 /* decr freq: 1ms ticks */ -#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ -#define CFG_BUS_CLK CFG_BUS_HZ +#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ +#define CONFIG_SYS_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ +#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#define CFG_TCLK 133000000 +#define CONFIG_SYS_TCLK 133000000 -/*#define CFG_750FX_HID0 0x8000c084*/ -#define CFG_750FX_HID0 0x80008484 -#define CFG_750FX_HID1 0x54800000 -#define CFG_750FX_HID2 0x00000000 +/*#define CONFIG_SYS_750FX_HID0 0x8000c084*/ +#define CONFIG_SYS_750FX_HID0 0x80008484 +#define CONFIG_SYS_750FX_HID1 0x54800000 +#define CONFIG_SYS_750FX_HID2 0x00000000 /* * Low Level Configuration Settings @@ -247,122 +257,128 @@ */ /* - * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS + * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS * To an unused memory region. The stack will remain in cache until RAM * is initialized */ -#undef CFG_INIT_RAM_LOCK -/* #define CFG_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */ -/* #define CFG_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */ -#define CFG_INIT_RAM_ADDR 0xf1080000 /* unused memory region */ -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#undef CONFIG_SYS_INIT_RAM_LOCK +/* #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */ +/* #define CONFIG_SYS_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */ +#define CONFIG_SYS_INIT_RAM_ADDR 0xf1080000 /* unused memory region */ +#define CONFIG_SYS_INIT_RAM_END 0x1000 +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) #define RELOCATE_INTERNAL_RAM_ADDR #ifdef RELOCATE_INTERNAL_RAM_ADDR -/*#define CFG_INTERNAL_RAM_ADDR 0xfba00000*/ -#define CFG_INTERNAL_RAM_ADDR 0xf1080000 +/*#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xfba00000*/ +#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf1080000 #endif /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Dummies for BAT 4-7 */ -#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#define CFG_SDRAM2_BASE 0x20000000 -#define CFG_SDRAM3_BASE 0x30000000 -#define CFG_SDRAM4_BASE 0x40000000 -#define CFG_RESET_ADDRESS 0xfff00100 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE 0xfff00000 -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */ +#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ +#define CONFIG_SYS_SDRAM2_BASE 0x20000000 +#define CONFIG_SYS_SDRAM3_BASE 0x30000000 +#define CONFIG_SYS_SDRAM4_BASE 0x40000000 +#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_BASE 0xfff00000 +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */ /*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CFG_FLASH_INCREMENT 0x01000000 /* there is only one bank */ -#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_BASE 0xfc000000 /* start of flash banks */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of flash banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */ +#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* size of flash bank */ +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_FLASH_BASE + 1*CONFIG_SYS_FLASH_INCREMENT, \ + CONFIG_SYS_FLASH_BASE + 2*CONFIG_SYS_FLASH_INCREMENT, \ + CONFIG_SYS_FLASH_BASE + 3*CONFIG_SYS_FLASH_INCREMENT } +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */ /* areas to map different things with the GT in physical space */ -#define CFG_DRAM_BANKS 4 +#define CONFIG_SYS_DRAM_BANKS 4 /* What to put in the bats. */ -#define CFG_MISC_REGION_BASE 0xf0000000 +#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 /* Peripheral Device section */ /*******************************************************/ -/* We have on the cpci750 Board : */ -/* GT-Chipset Register Area */ -/* GT-Chipset internal SRAM 256k */ -/* SRAM on external device module */ -/* Real time clock on external device module */ -/* dobble UART on external device module */ -/* Data flash on external device module */ -/* Boot flash on external device module */ +/* We have on the cpci750 Board : */ +/* GT-Chipset Register Area */ +/* GT-Chipset internal SRAM 256k */ +/* SRAM on external device module */ +/* Real time clock on external device module */ +/* dobble UART on external device module */ +/* Data flash on external device module */ +/* Boot flash on external device module */ /*******************************************************/ -#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ -#define CFG_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */ +#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ +#define CONFIG_SYS_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */ -#undef MARVEL_STANDARD_CFG -#ifndef MARVEL_STANDARD_CFG +#undef MARVEL_STANDARD_CFG +#ifndef MARVEL_STANDARD_CFG /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ -/*#define CFG_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */ -#define CFG_INT_SRAM_BASE 0xf1080000 /* GT offers 256k internal fast SRAM */ - -#define CFG_BOOT_SPACE 0xff000000 /* BOOT_CS0 flash 0 */ -#define CFG_DEV0_SPACE 0xfc000000 /* DEV_CS0 flash 1 */ -#define CFG_DEV1_SPACE 0xfd000000 /* DEV_CS1 flash 2 */ -#define CFG_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */ -#define CFG_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */ - -#define CFG_BOOT_SIZE _16M /* cpci750 flash 0 */ -#define CFG_DEV0_SIZE _16M /* cpci750 flash 1 */ -#define CFG_DEV1_SIZE _16M /* cpci750 flash 2 */ -#define CFG_DEV2_SIZE _16M /* cpci750 flash 3 */ -#define CFG_DEV3_SIZE _16M /* cpci750 nvram/can */ +#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ +/*#define CONFIG_SYS_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */ +#define CONFIG_SYS_INT_SRAM_BASE 0xf1080000 /* GT offers 256k internal fast SRAM */ + +#define CONFIG_SYS_BOOT_SPACE 0xff000000 /* BOOT_CS0 flash 0 */ +#define CONFIG_SYS_DEV0_SPACE 0xfc000000 /* DEV_CS0 flash 1 */ +#define CONFIG_SYS_DEV1_SPACE 0xfd000000 /* DEV_CS1 flash 2 */ +#define CONFIG_SYS_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */ +#define CONFIG_SYS_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */ + +#define CONFIG_SYS_BOOT_SIZE _16M /* cpci750 flash 0 */ +#define CONFIG_SYS_DEV0_SIZE _16M /* cpci750 flash 1 */ +#define CONFIG_SYS_DEV1_SIZE _16M /* cpci750 flash 2 */ +#define CONFIG_SYS_DEV2_SIZE _16M /* cpci750 flash 3 */ +#define CONFIG_SYS_DEV3_SIZE _16M /* cpci750 nvram/can */ /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ #endif /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ -#define CFG_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CFG_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CFG_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CFG_DEV3_PAR 0x8FCFFFFF /* nvram/can */ -#define CFG_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */ - - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ +#define CONFIG_SYS_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */ +#define CONFIG_SYS_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */ +#define CONFIG_SYS_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */ +#define CONFIG_SYS_DEV3_PAR 0x8FCFFFFF /* nvram/can */ +#define CONFIG_SYS_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */ + + /* c 4 a 8 2 4 1 c */ + /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ /* MPP Control MV64360 Appendix P P. 632*/ -#define CFG_MPP_CONTROL_0 0x00002222 /* */ -#define CFG_MPP_CONTROL_1 0x11110000 /* */ -#define CFG_MPP_CONTROL_2 0x11111111 /* */ -#define CFG_MPP_CONTROL_3 0x00001111 /* */ -/* #define CFG_SERIAL_PORT_MUX 0x00000102*/ /* */ +#define CONFIG_SYS_MPP_CONTROL_0 0x00002222 /* */ +#define CONFIG_SYS_MPP_CONTROL_1 0x11110000 /* */ +#define CONFIG_SYS_MPP_CONTROL_2 0x11111111 /* */ +#define CONFIG_SYS_MPP_CONTROL_3 0x00001111 /* */ +/* #define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102*/ /* */ -#define CFG_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/ +#define CONFIG_SYS_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/ /* setup new config_value for MV64360 DDR-RAM To_do !! */ -/*# define CFG_SDRAM_CONFIG 0xd8e18200*/ /* 0x448 */ -/*# define CFG_SDRAM_CONFIG 0xd8e14400*/ /* 0x1400 */ +/*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200*/ /* 0x448 */ +/*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e14400*/ /* 0x1400 */ /* GB has high prio. idma has low prio MPSC has low prio @@ -372,13 +388,13 @@ ECC disable non registered DRAM */ /* 31:26 25:22 21:20 19 18 17 16 */ - /* 100001 0000 010 0 0 0 0 */ + /* 100001 0000 010 0 0 0 0 */ /* refresh_count=0x400 phisical interleaving disable virtual interleaving enable */ /* 15 14 13:0 */ - /* 0 1 0x400 */ -# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ + /* 0 1 0x400 */ +# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ /*----------------------------------------------------------------------- @@ -386,62 +402,62 @@ *----------------------------------------------------------------------- */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ /* PCI MEMORY MAP section */ -#define CFG_PCI0_MEM_BASE 0x80000000 -#define CFG_PCI0_MEM_SIZE _128M -#define CFG_PCI1_MEM_BASE 0x88000000 -#define CFG_PCI1_MEM_SIZE _128M +#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI0_MEM_SIZE _128M +#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 +#define CONFIG_SYS_PCI1_MEM_SIZE _128M -#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) -#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) +#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) +#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) /* PCI I/O MAP section */ -#define CFG_PCI0_IO_BASE 0xfa000000 -#define CFG_PCI0_IO_SIZE _16M -#define CFG_PCI1_IO_BASE 0xfb000000 -#define CFG_PCI1_IO_SIZE _16M +#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 +#define CONFIG_SYS_PCI0_IO_SIZE _16M +#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 +#define CONFIG_SYS_PCI1_IO_SIZE _16M -#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) -#define CFG_PCI0_IO_SPACE_PCI 0x00000000 -#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) -#define CFG_PCI1_IO_SPACE_PCI 0x00000000 +#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) +#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 +#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) +#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 -#define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE) +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE) #if defined (CONFIG_750CX) -#define CFG_PCI_IDSEL 0x0 +#define CONFIG_SYS_PCI_IDSEL 0x0 #else -#define CFG_PCI_IDSEL 0x30 +#define CONFIG_SYS_PCI_IDSEL 0x30 #endif /*----------------------------------------------------------------------- * IDE/ATA stuff *----------------------------------------------------------------------- */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET /* no reset for ide supported */ -#define CONFIG_IDE_PREINIT /* check for units */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#define CONFIG_IDE_RESET /* no reset for ide supported */ +#define CONFIG_IDE_PREINIT /* check for units */ -#define CFG_IDE_MAXBUS 2 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */ +#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 1 IDE busses */ +#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */ -#define CFG_ATA_BASE_ADDR 0 -#define CFG_ATA_IDE0_OFFSET 0 -#define CFG_ATA_IDE1_OFFSET 0 +#define CONFIG_SYS_ATA_BASE_ADDR 0 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0 -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ +#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ +#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ /*---------------------------------------------------------------------- @@ -454,28 +470,28 @@ */ /* SDRAM */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT0U CFG_IBAT0U +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U /* init ram */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U /* PCI0, PCI1 in one BAT */ -#define CFG_IBAT2L BATL_NO_ACCESS -#define CFG_IBAT2U CFG_DBAT2U -#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS +#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) /* GT regs, bootrom, all the devices, PCI I/O */ -#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U CFG_IBAT3U +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7) @@ -486,52 +502,52 @@ /*#define SETUP_HIGH_BATS_FX750*/ /* initialize BATS 4-7 */ #ifdef SETUP_HIGH_BATS_FX750 -#define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT4U CFG_IBAT4U +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U /* IBAT5 and DBAT5 */ -#define CFG_IBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT5U (CFG_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT5U CFG_IBAT5U +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U /* IBAT6 and DBAT6 */ -#define CFG_IBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT6U (CFG_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT6U CFG_IBAT6U +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U /* IBAT7 and DBAT7 */ -#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT7U CFG_IBAT7U +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U #else /* set em out of range for Linux !!!!!!!!!!! */ -#define CFG_IBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT4U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT4U CFG_IBAT4U +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U /* IBAT5 and DBAT5 */ -#define CFG_IBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT5U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT5U CFG_IBAT4U +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT4U /* IBAT6 and DBAT6 */ -#define CFG_IBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT6U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT6U CFG_IBAT4U +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT4U /* IBAT7 and DBAT7 */ -#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT7U CFG_IBAT4U +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT4U #endif /* FIXME: ingo end: disable BATs for Linux Kernel */ @@ -545,42 +561,42 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_BOOT_FLASH_WIDTH 2 /* 16 bit */ +#define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ #if 0 -#define CFG_ENV_IS_IN_FLASH 0 -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x10000 -#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ -/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ +/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */ #endif -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_EEPROM_PAGE_WRITE_BITS 5 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CFG_I2C_EEPROM_ADDR 0x050 -#define CFG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/ +#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x050 +#define CONFIG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */ +#define CONFIG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/ -#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40) +#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ +#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ +#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-0x40) /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif /*----------------------------------------------------------------------- @@ -588,14 +604,14 @@ * look in include/mpc74xx.h for the defines used here */ -/*#define CFG_L2*/ -#undef CFG_L2 +/*#define CONFIG_SYS_L2*/ +#undef CONFIG_SYS_L2 /* #ifdef CONFIG_750CX*/ #if defined (CONFIG_750CX) || defined (CONFIG_750FX) #define L2_INIT 0 #else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) #endif @@ -606,9 +622,11 @@ * * Boot Flags */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_BOARD_ASM_INIT 1 +#define CONFIG_SYS_BOARD_ASM_INIT 1 + +#define CPCI750_SLAVE_TEST (((in8(0xf0300000) & 0x80) == 0) ? 0 : 1) #endif /* __CONFIG_H */