X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FCPU86.h;h=ab64adae0e995ab4edb5763806259ba5eaef20b5;hb=95e39793312ab1ce01615f2b5330382e99ed6e81;hp=6d76d9ff8d4d909183ca8f87d3154a9d253e6752;hpb=84efbf4d144ff8aaed3cca036aebb1fe69eff3f4;p=u-boot

diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
index 6d76d9ff8d..ab64adae0e 100644
--- a/include/configs/CPU86.h
+++ b/include/configs/CPU86.h
@@ -37,6 +37,12 @@
 #define CONFIG_CPU86		1	/* ...on a CPU86 board	*/
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
+#ifdef CONFIG_BOOT_ROM
+#define CONFIG_SYS_TEXT_BASE	0xFF800000
+#else
+#define	CONFIG_SYS_TEXT_BASE	0xFF000000
+#endif
+
 /*
  * select serial console configuration
  *
@@ -290,9 +296,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000  /* Size of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -304,7 +309,7 @@
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #define CONFIG_SYS_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
 #define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
 
@@ -333,15 +338,6 @@
 #define CONFIG_ENV_SIZE		(2048 - 512)
 #endif
 
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot                 */
-
-
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */