X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FDU405.h;h=9be2310dbdf3243a4954803b8ea35f0481a38db1;hb=61b57c4ab93a2dc6c7dd4e96e85543d2aafffe9c;hp=d1edd244b4ef71174a159fb62516c410df513c23;hpb=8206bfae3ab7f99965136384360ba2de0c6f4c3b;p=u-boot diff --git a/include/configs/DU405.h b/include/configs/DU405.h index d1edd244b4..9be2310dbd 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -2,23 +2,7 @@ * (C) Copyright 2001 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -33,9 +17,10 @@ * (easy to change) */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_DU405 1 /* ...on a DU405 board */ +#define CONFIG_SYS_TEXT_BASE 0xFFFD0000 + #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ @@ -55,7 +40,6 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ -#define CONFIG_NET_MULTI 1 #undef CONFIG_HAS_ETH1 /* @@ -73,6 +57,11 @@ #include #undef CONFIG_CMD_NFS +#undef CONFIG_CMD_EDITENV +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_CONSOLE +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS #define CONFIG_CMD_IDE #define CONFIG_CMD_ELF #define CONFIG_CMD_MII @@ -94,7 +83,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -109,6 +97,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */ /* The following table includes the supported baudrates */ @@ -119,38 +113,10 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffe00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - /*----------------------------------------------------------------------- * IDE/ATA stuff *----------------------------------------------------------------------- @@ -211,10 +177,11 @@ /*----------------------------------------------------------------------- * I2C EEPROM (CAT24WC08) for environment */ -#define CONFIG_I2C_CMD_TREE 1 -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_PPC4XX +#define CONFIG_SYS_I2C_PPC4XX_CH0 +#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 +#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ @@ -299,18 +266,8 @@ #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - #endif /* __CONFIG_H */