X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FEB%2BMCF-EV123.h;h=720b335b099158ce83733ab331c4ee63c53a442b;hb=8d7e2732221bc2d64df14f700c64c23e0a4c3dce;hp=f49a4b74518e4db798097a266031d0b88a5c5fba;hpb=4176c799645d8b35224345d899006993397635c1;p=u-boot

diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
index f49a4b7451..720b335b09 100644
--- a/include/configs/EB+MCF-EV123.h
+++ b/include/configs/EB+MCF-EV123.h
@@ -30,7 +30,7 @@
 #undef DEBUG
 #undef CFG_HALT_BEFOR_RAM_JUMP
 #undef ET_DEBUG
-  
+
 /*
  * High Level Configuration Options (easy to change)
  */
@@ -68,7 +68,7 @@
 #define CFG_ENV_IS_IN_FLASH	1
 #endif
 
-//#define CONFIG_COMMANDS  ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) )
+/*#define CONFIG_COMMANDS  ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) ) */
 #define CONFIG_COMMANDS  ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADB))
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -95,12 +95,12 @@
 #undef CFG_DRAM_TEST
 
 /* Clock and PLL Configuration */
-#define CFG_HZ			10000000 
+#define CFG_HZ			10000000
 #define	CFG_CLK			58982400       /* 9,8304MHz * 6 */
 
 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
 
-#define CFG_MFD			0x01	/* PLL Multiplication Factor Devider */	
+#define CFG_MFD			0x01	/* PLL Multiplication Factor Devider */
 #define CFG_RFD			0x00	/* PLL Reduce Frecuency Devider */
 
 /*
@@ -143,7 +143,7 @@
 /* If M5282 port is fully implemented the monitor base will be behind
  * the vector table. */
 #if (TEXT_BASE !=  CFG_INT_FLASH_BASE)
-#define CFG_MONITOR_BASE	(TEXT_BASE + 0x400) 
+#define CFG_MONITOR_BASE	(TEXT_BASE + 0x400)
 #else
 #define CFG_MONITOR_BASE	(TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
 #endif