X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FHH405.h;h=444413d8d6646545fed0227a42d66cd7d30feba2;hb=59ee45ee91cc91b392a8e2684bfcb8c933ce4967;hp=ed9a235f6e52f61e27589f4d6057add44d1ea6af;hpb=91f33534728e6416d332ad2b53ad1d6fde57f7fc;p=u-boot

diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index ed9a235f6e..444413d8d6 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -43,6 +43,8 @@
 #define CONFIG_4xx		1	/* ...member of PPC4xx family   */
 #define CONFIG_HH405		1	/* ...on a HH405 board	        */
 
+#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
+
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
 
@@ -65,7 +67,6 @@
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_PPC4xx_EMAC
-#define CONFIG_NET_MULTI	1
 #undef  CONFIG_HAS_ETH1
 
 #define CONFIG_MII		1	/* MII PHY management		*/
@@ -154,9 +155,6 @@
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CONFIG_SYS_HUSH_PARSER
-#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-#endif
 
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
@@ -176,9 +174,14 @@
 #define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
+#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* no external serial clock used */
 #define CONFIG_SYS_BASE_BAUD       691200
-#define CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
 
 /* The following table includes the supported baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE      \
@@ -306,7 +309,7 @@
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #define CONFIG_SYS_FLASH_BASE		0xFFF80000
-#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
 #define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* Reserve 4 MB for malloc()	*/
 
@@ -331,6 +334,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #if 0 /* test-only */
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #else
@@ -413,23 +417,6 @@
 
 #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100       /* FPGA internal Base Address       */
 
-/* FPGA internal regs */
-#define CONFIG_SYS_FPGA_CTRL           0x000
-
-/* FPGA Control Reg */
-#define CONFIG_SYS_FPGA_CTRL_REV0      0x0001
-#define CONFIG_SYS_FPGA_CTRL_REV1      0x0002
-#define CONFIG_SYS_FPGA_CTRL_VGA0_BL   0x0004
-#define CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE 0x0008
-#define CONFIG_SYS_FPGA_CTRL_CF_RESET  0x0040
-#define CONFIG_SYS_FPGA_CTRL_PS2_PWR   0x0080
-#define CONFIG_SYS_FPGA_CTRL_CF_PWRN   0x0100      /* low active                    */
-#define CONFIG_SYS_FPGA_CTRL_CF_BUS_EN 0x0200
-#define CONFIG_SYS_FPGA_CTRL_LCD_CLK   0x7000      /* Mask for lcd clock            */
-#define CONFIG_SYS_FPGA_CTRL_OW_ENABLE 0x8000
-
-#define CONFIG_SYS_FPGA_STATUS_CF_DETECT 0x8000
-
 #define LCD_CLK_OFF             0x0000      /* Off                           */
 #define LCD_CLK_02083           0x1000      /* 2.083 MHz                     */
 #define LCD_CLK_03135           0x2000      /* 3.135 MHz                     */
@@ -459,10 +446,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -477,12 +463,12 @@
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  */
-#define CONFIG_SYS_GPIO0_OSRH		0x40000550
-#define CONFIG_SYS_GPIO0_OSRL		0x00000110
-#define CONFIG_SYS_GPIO0_ISR1H		0x00000000
-#define CONFIG_SYS_GPIO0_ISR1L		0x15555440
-#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_OSRL		0x40000550
+#define CONFIG_SYS_GPIO0_OSRH		0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L		0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H		0x15555440
 #define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
 #define CONFIG_SYS_GPIO0_TCR		0xF7FE0017
 
 #define CONFIG_SYS_LCD_ENDIAN		(0x80000000 >> 7)
@@ -491,14 +477,6 @@
 #define CONFIG_SYS_LCD0_RST		(0x80000000 >> 30)
 #define CONFIG_SYS_LCD1_RST		(0x80000000 >> 31)
 
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
 /*
  * Default speed selection (cpu_plb_opb_ebc) in mhz.
  * This value will be set if iic boot eprom is disabled.