X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FHH405.h;h=92335239df2fe2e9c6e42c8d734411b3b6cb11e8;hb=f52efcae98cbb8a39f1d0535df8d9646a776af9e;hp=ed9a235f6e52f61e27589f4d6057add44d1ea6af;hpb=91f33534728e6416d332ad2b53ad1d6fde57f7fc;p=u-boot

diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index ed9a235f6e..92335239df 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -413,23 +413,6 @@
 
 #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100       /* FPGA internal Base Address       */
 
-/* FPGA internal regs */
-#define CONFIG_SYS_FPGA_CTRL           0x000
-
-/* FPGA Control Reg */
-#define CONFIG_SYS_FPGA_CTRL_REV0      0x0001
-#define CONFIG_SYS_FPGA_CTRL_REV1      0x0002
-#define CONFIG_SYS_FPGA_CTRL_VGA0_BL   0x0004
-#define CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE 0x0008
-#define CONFIG_SYS_FPGA_CTRL_CF_RESET  0x0040
-#define CONFIG_SYS_FPGA_CTRL_PS2_PWR   0x0080
-#define CONFIG_SYS_FPGA_CTRL_CF_PWRN   0x0100      /* low active                    */
-#define CONFIG_SYS_FPGA_CTRL_CF_BUS_EN 0x0200
-#define CONFIG_SYS_FPGA_CTRL_LCD_CLK   0x7000      /* Mask for lcd clock            */
-#define CONFIG_SYS_FPGA_CTRL_OW_ENABLE 0x8000
-
-#define CONFIG_SYS_FPGA_STATUS_CF_DETECT 0x8000
-
 #define LCD_CLK_OFF             0x0000      /* Off                           */
 #define LCD_CLK_02083           0x1000      /* 2.083 MHz                     */
 #define LCD_CLK_03135           0x2000      /* 3.135 MHz                     */