X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FHH405.h;h=dc40ebc861d715e6a65684db2631761b12957404;hb=dcaa71562826a2466e894c868d132509dcda8444;hp=9ce6b3f8914a4f810fd251a12f01585546e99168;hpb=a6e6cf00367c0779eadb49915e40c55f0a787957;p=u-boot

diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index 9ce6b3f891..dc40ebc861 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -5,6 +5,9 @@
  * (C) Copyright 2005
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
+ * (C) Copyright 2006
+ * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -55,24 +58,35 @@
 
 #define CONFIG_PREBOOT	        "autoupd"
 
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"pciconfighost=1\0"						\
+	""
+
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#define CONFIG_NET_MULTI	1
+#undef  CONFIG_HAS_ETH1
+
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
 
 #define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
 
 /*
  * Video console
  */
-#define CONFIG_VIDEO
+#define CONFIG_VIDEO			/* for sm501 video support	*/
+
+#ifdef CONFIG_VIDEO
 #define CONFIG_VIDEO_SM501
 #if 0
 #define CONFIG_VIDEO_SM501_32BPP
 #else
 #define CONFIG_VIDEO_SM501_16BPP
 #endif
+#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VGA_AS_SINGLE_DEVICE
@@ -82,13 +96,12 @@
 #define CFG_CONSOLE_IS_IN_ENV
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_VIDEO_BMP_GZIP		/* gzip compressed bmp images	*/
-#define CFG_VIDEO_LOGO_MAX_SIZE	(1024*1024)	/* for decompressed img */
+#define CFG_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* for decompressed img */
 
-#ifdef CONFIG_VIDEO
 #define ADD_BMP_CMD		CFG_CMD_BMP
 #else
 #define ADD_BMP_CMD		0
-#endif
+#endif /* CONFIG_VIDEO */
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \
@@ -117,6 +130,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 #undef  CONFIG_BZIP2	 /* include support for bzip2 compressed images */
 #undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -303,7 +318,7 @@
 #define CFG_FLASH_BASE		0xFFF80000
 #define CFG_MONITOR_BASE	TEXT_BASE
 #define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(2 * 1024*1024)	/* Reserve 2 MB for malloc()	*/
+#define CFG_MALLOC_LEN		(4 << 20)	/* Reserve 4 MB for malloc()	*/
 
 #if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
 # define CFG_RAMBOOT		1
@@ -359,7 +374,7 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's    */
 					/* have only 8kB, 16kB is save here     */
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
@@ -404,8 +419,6 @@
 #define CFG_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
 #define CFG_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */
 
-#define CFG_LCD_LOGO_MAX_SIZE   (1024*1024)
-
 /*-----------------------------------------------------------------------
  * Universal Interrupt Controller (UIC) Setup
  */
@@ -431,9 +444,12 @@
 #define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008
 #define CFG_FPGA_CTRL_CF_RESET  0x0040
 #define CFG_FPGA_CTRL_PS2_PWR   0x0080
-#define CFG_FPGA_CTRL_CF_PWR    0x0100      /* low active                    */
+#define CFG_FPGA_CTRL_CF_PWRN   0x0100      /* low active                    */
 #define CFG_FPGA_CTRL_CF_BUS_EN 0x0200
 #define CFG_FPGA_CTRL_LCD_CLK   0x7000      /* Mask for lcd clock            */
+#define CFG_FPGA_CTRL_OW_ENABLE 0x8000
+
+#define CFG_FPGA_STATUS_CF_DETECT 0x8000
 
 #define LCD_CLK_OFF             0x0000      /* Off                           */
 #define LCD_CLK_02083           0x1000      /* 2.083 MHz                     */