X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FM5249EVB.h;h=ae4fe45fce4ea9091da308da6d21931363f29a71;hb=42817eb85de1d7dec399c75dbd133ea6b5351a72;hp=8699ef98ee12a96f2f5c52301dbbb4422fc61d2e;hpb=50bd0057ba8fceeb48533f8b1a652ccd0e170838;p=u-boot

diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index 8699ef98ee..ae4fe45fce 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -4,23 +4,7 @@
  * (C) Copyright 2004
  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /*
@@ -42,7 +26,6 @@
 #define CONFIG_MCFUART
 #define CONFIG_SYS_UART_PORT		(0)
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef  CONFIG_WATCHDOG
 
@@ -60,9 +43,9 @@
  * Command line configuration.
  */
 #include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
 #undef CONFIG_CMD_NET
 
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
 
 #if defined(CONFIG_CMD_KGDB)
@@ -85,8 +68,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x400
 #define CONFIG_SYS_MEMTEST_END		0x380000
 
-#define CONFIG_SYS_HZ			1000
-
 /*
  * Clock configuration: enable only one of the following options
  */
@@ -108,9 +89,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_ENV_IS_IN_FLASH	1
@@ -125,7 +105,7 @@
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CSAR0 << 16)
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
 
 #if 0 /* test-only */
 #define CONFIG_PRAM		512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
@@ -165,20 +145,34 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+					 CF_ADDRMASK(2) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
 
 /* CS0 - AMD Flash, address 0xffc00000 */
-#define	CONFIG_SYS_CSAR0		0xffe0
-#define	CONFIG_SYS_CSCR0		0x1980		/* WS=0110, AA=1, PS=10         */
+#define	CONFIG_SYS_CS0_BASE		0xffe00000
+#define	CONFIG_SYS_CS0_CTRL		0x00001980	/* WS=0110, AA=1, PS=10         */
 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
-#define	CONFIG_SYS_CSMR0		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
+#define	CONFIG_SYS_CS0_MASK		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
 
 /* CS1 - FPGA, address 0xe0000000 */
-#define	CONFIG_SYS_CSAR1		0xe000
-#define	CONFIG_SYS_CSCR1		0x0d80		/* WS=0011, AA=1, PS=10         */
-#define	CONFIG_SYS_CSMR1		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
+#define	CONFIG_SYS_CS1_BASE		0xe0000000
+#define	CONFIG_SYS_CS1_CTRL		0x00000d80	/* WS=0011, AA=1, PS=10         */
+#define	CONFIG_SYS_CS1_MASK		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
 
 /*-----------------------------------------------------------------------
  * Port configuration