X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FM5253DEMO.h;h=5d978747fe8ae5fc8faac0261aa607563f0275ed;hb=0d1ea05210f3221667f8085cf167f23f336ca0c0;hp=3a5c12faa46f9988aeb24f47af989d502186191d;hpb=f82642e33899766892499b163e60560fbbf87773;p=u-boot diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 3a5c12faa4..5d978747fe 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -1,31 +1,12 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. +/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * Hayden Fraser (Hayden.Fraser@freescale.com) * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _M5253DEMO_H #define _M5253DEMO_H -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5253 /* define processor type */ #define CONFIG_M5253DEMO /* define board type */ #define CONFIG_MCFTMR @@ -33,7 +14,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } #undef CONFIG_WATCHDOG /* disable watchdog */ @@ -52,11 +32,16 @@ # define CONFIG_ENV_IS_IN_FLASH 1 #endif +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text*); + /* * Command line configuration. */ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_LOADB #define CONFIG_CMD_LOADS #define CONFIG_CMD_EXT2 @@ -85,33 +70,28 @@ # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ -# define _IO_BASE 0 #endif #define CONFIG_DRIVER_DM9000 #ifdef CONFIG_DRIVER_DM9000 -# define CONFIG_DM9000_BASE ((CONFIG_SYS_CSAR1 << 16) | 0x300) +# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) # define DM9000_IO CONFIG_DM9000_BASE # define DM9000_DATA (CONFIG_DM9000_BASE + 4) # undef CONFIG_DM9000_DEBUG +# define CONFIG_DM9000_BYTE_SWAPPED -# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 -# define CONFIG_IPADDR 10.82.121.249 -# define CONFIG_NETMASK 255.255.252.0 -# define CONFIG_SERVERIP 10.82.120.80 -# define CONFIG_GATEWAYIP 10.82.123.254 # define CONFIG_OVERWRITE_ETHADDR_ONCE # define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ - "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \ + "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ "loadaddr=10000\0" \ "u-boot=u-boot.bin\0" \ "load=tftp ${loadaddr) ${u-boot}\0" \ "upd=run load; run prog\0" \ - "prog=prot off 0 2ffff;" \ - "era 0 2ffff;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ + "prog=prot off 0xff800000 0xff82ffff;" \ + "era 0xff800000 0xff82ffff;" \ + "cp.b ${loadaddr} 0xff800000 ${filesize};" \ "save\0" \ "" #endif @@ -119,17 +99,16 @@ #define CONFIG_HOSTNAME M5253DEMO /* I2C */ -#define CONFIG_FSL_I2C -#define CONFIG_HARD_I2C /* I2C with hw support */ -#define CONFIG_SYS_I2C_SPEED 80000 -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_OFFSET 0x00000280 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 80000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) #define CONFIG_SYS_I2C_PINMUX_SET (0) -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_LONGHELP /* undef to save memory */ #if defined(CONFIG_CMD_KGDB) @@ -146,8 +125,6 @@ #define CONFIG_SYS_MEMTEST_START 0x400 #define CONFIG_SYS_MEMTEST_END 0x380000 -#define CONFIG_SYS_HZ 1000 - #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ #define CONFIG_SYS_FAST_CLK #ifdef CONFIG_SYS_FAST_CLK @@ -171,9 +148,8 @@ * Definitions for initial stack pointer and data area (in DPRAM) */ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* @@ -200,9 +176,10 @@ * the maximum mapped by the Linux kernel during initialization ?? */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /* FLASH organization */ -#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CSAR0 << 16) +#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 @@ -230,24 +207,30 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ + CF_ADDRMASK(8) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ + CF_CACR_DBWE) + /* Port configuration */ #define CONFIG_SYS_FECI2C 0xF0 -#define CONFIG_SYS_CSAR0 0xFF80 -#define CONFIG_SYS_CSMR0 0x007F0021 -#define CONFIG_SYS_CSCR0 0x1D80 - -#define CONFIG_SYS_CSAR1 0xE000 -#define CONFIG_SYS_CSMR1 0x00000001 -#define CONFIG_SYS_CSCR1 0x3DD8 - -#define CONFIG_SYS_CSAR2 0 -#define CONFIG_SYS_CSMR2 0 -#define CONFIG_SYS_CSCR2 0 +#define CONFIG_SYS_CS0_BASE 0xFF800000 +#define CONFIG_SYS_CS0_MASK 0x007F0021 +#define CONFIG_SYS_CS0_CTRL 0x00001D80 -#define CONFIG_SYS_CSAR3 0 -#define CONFIG_SYS_CSMR3 0 -#define CONFIG_SYS_CSCR3 0 +#define CONFIG_SYS_CS1_BASE 0xE0000000 +#define CONFIG_SYS_CS1_MASK 0x00000001 +#define CONFIG_SYS_CS1_CTRL 0x00003DD8 /*----------------------------------------------------------------------- * Port configuration