X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FM54455EVB.h;h=806f00555f98503d16f5226d0de1040b49940564;hb=e38f5fc8d80d946b401ba0e9ba0fcb52d6e7e74b;hp=3dc87d6f61a08feb49514dec716c6f5bb473c6db;hpb=8b485ba12b0defa0c4ed3559789250238f8331a8;p=u-boot diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 3dc87d6f61..806f00555f 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -4,7 +4,7 @@ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -18,13 +18,10 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF5445x /* define processor family */ -#define CONFIG_M54455 /* define processor type */ #define CONFIG_M54455EVB /* M54455EVB board */ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 #undef CONFIG_WATCHDOG @@ -39,31 +36,10 @@ #define CONFIG_BOOTP_HOSTNAME /* Command line configuration */ -#include - -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_I2C #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET #undef CONFIG_CMD_PCI -#define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF - -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_LOADS /* Network configuration */ #define CONFIG_MCFFEC @@ -81,16 +57,12 @@ # define MCFFEC_TOUT_LOOP 50000 # define CONFIG_HAS_ETH1 -# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" -# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 -# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 # define CONFIG_ETHPRIME "FEC0" # define CONFIG_IPADDR 192.162.1.2 # define CONFIG_NETMASK 255.255.255.0 # define CONFIG_SERVERIP 192.162.1.1 # define CONFIG_GATEWAYIP 192.162.1.1 -# define CONFIG_OVERWRITE_ETHADDR_ONCE /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ # ifndef CONFIG_SYS_DISCOVER_PHY @@ -145,8 +117,6 @@ #endif /* ATA configuration */ -#define CONFIG_ISO_PARTITION -#define CONFIG_DOS_PARTITION #define CONFIG_IDE_RESET 1 #define CONFIG_IDE_PREINIT 1 #define CONFIG_ATAPI @@ -177,7 +147,7 @@ #define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 80000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSLI2C_OFFSET 0x58000 +#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR /* DSPI and Serial Flash */ @@ -186,8 +156,6 @@ #define CONFIG_HARD_SPI #define CONFIG_SYS_SBFHDR_SIZE 0x13 #ifdef CONFIG_CMD_SPI -# define CONFIG_SPI_FLASH -# define CONFIG_SPI_FLASH_STMICRO # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ DSPI_CTAR_PCSSCK_1CLK | \ @@ -200,8 +168,6 @@ /* PCI */ #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 @@ -232,7 +198,6 @@ #define CONFIG_PRAM 2048 /* 2048 KB */ -#define CONFIG_SYS_PROMPT "-> " #define CONFIG_SYS_LONGHELP /* undef to save memory */ #if defined(CONFIG_CMD_KGDB) @@ -246,8 +211,6 @@ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) -#define CONFIG_SYS_HZ 1000 - #define CONFIG_SYS_MBAR 0xFC000000 /*