X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FM54455EVB.h;h=b623c33318aa918391f04d6b3d780955da51918d;hb=495dbd72dd1172de866ba323263a5b62cf454972;hp=101dcedeed1cb95d596b120b6de95e5979ac17b3;hpb=6d0f6bcf337c5261c08fabe12982178c2c489d76;p=u-boot diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 101dcedeed..b623c33318 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -41,7 +41,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } #undef CONFIG_WATCHDOG @@ -85,7 +84,6 @@ /* Network configuration */ #define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC -# define CONFIG_NET_MULTI 1 # define CONFIG_MII 1 # define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY @@ -134,7 +132,7 @@ "load=tftp ${loadaddr} ${sbfhdr};" \ "tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ "upd=run load; run prog\0" \ - "prog=sf probe 0:1 10000 1;" \ + "prog=sf probe 0:1 1000000 3;" \ "sf erase 0 30000;" \ "sf write ${loadaddr} 0 0x30000;" \ "save\0" \ @@ -180,7 +178,6 @@ #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ -#define _IO_BASE 0 /* Realtime clock */ #define CONFIG_MCFRTC @@ -201,25 +198,21 @@ #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR /* DSPI and Serial Flash */ +#define CONFIG_CF_SPI #define CONFIG_CF_DSPI #define CONFIG_HARD_SPI -#define CONFIG_SYS_SER_FLASH_BASE 0x01000000 #define CONFIG_SYS_SBFHDR_SIZE 0x13 #ifdef CONFIG_CMD_SPI # define CONFIG_SPI_FLASH # define CONFIG_SPI_FLASH_STMICRO -# define CONFIG_SYS_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \ - DSPI_DCTAR_CPOL | \ - DSPI_DCTAR_CPHA | \ - DSPI_DCTAR_PCSSCK_1CLK | \ - DSPI_DCTAR_PASC(0) | \ - DSPI_DCTAR_PDT(0) | \ - DSPI_DCTAR_CSSCK(0) | \ - DSPI_DCTAR_ASC(0) | \ - DSPI_DCTAR_PBR(0) | \ - DSPI_DCTAR_DT(1) | \ - DSPI_DCTAR_BR(1)) +# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ + DSPI_CTAR_PCSSCK_1CLK | \ + DSPI_CTAR_PASC(0) | \ + DSPI_CTAR_PDT(0) | \ + DSPI_CTAR_CSSCK(0) | \ + DSPI_CTAR_ASC(0) | \ + DSPI_CTAR_DT(1)) #endif /* PCI */ @@ -284,12 +277,11 @@ * Definitions for initial stack pointer and data area (in DPRAM) */ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32) +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - 32) +#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -310,13 +302,16 @@ #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) #ifdef CONFIG_CF_SBF -# define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400) +# define CONFIG_SERIAL_BOOT +# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) #else # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) #endif #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* Reserve 256 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* * For booting Linux, the board info and command line data @@ -328,7 +323,8 @@ /* * Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash + * Environment is not embedded in u-boot. First time runing may have env + * crc error warning if there is no correct environment on the flash. */ #ifdef CONFIG_CF_SBF # define CONFIG_ENV_IS_IN_SPI_FLASH @@ -337,16 +333,13 @@ # define CONFIG_ENV_IS_IN_FLASH 1 #endif #undef CONFIG_ENV_OVERWRITE -#undef CONFIG_ENV_IS_EMBEDDED /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_STMICRO_BOOT -# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SER_FLASH_BASE -# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_SER_FLASH_BASE -# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH2_BASE CONFIG_SYS_CS1_BASE +# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE # define CONFIG_ENV_OFFSET 0x30000 # define CONFIG_ENV_SIZE 0x2000 # define CONFIG_ENV_SECT_SIZE 0x10000 @@ -355,8 +348,9 @@ # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) -# define CONFIG_ENV_SECT_SIZE 0x2000 +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) +# define CONFIG_ENV_SIZE 0x2000 +# define CONFIG_ENV_SECT_SIZE 0x10000 #endif #ifdef CONFIG_SYS_INTEL_BOOT # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE @@ -371,6 +365,7 @@ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_FLASH_CFI_DRIVER 1 +# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ @@ -415,6 +410,21 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ + CF_CACR_ICINVA | CF_CACR_EUSP) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + /*----------------------------------------------------------------------- * Memory bank definitions */