X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FMIP405.h;h=9961fb55ca509c3e6c6381bad334837e21ef4dd8;hb=877012df309329a9264e6e9558d4f71bfa0cddbe;hp=ce9273b6f7d06cb3299759dcc7a71f39739d2814;hpb=1032d97496f6d534bf0030a5779ff1cb38cc9ebf;p=u-boot

diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index ce9273b6f7..9961fb55ca 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -239,11 +239,17 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_UPDATE_FLASH_SIZE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
 
 /*
  * JFFS2 partitions
@@ -291,6 +297,7 @@
 #define FLASH_SIZE_PRELIM	 3  /* maximal flash FLASH size bank #0	*/
 
 #define CONFIG_BOARD_EARLY_INIT_F 1
+#define CONFIG_BOARD_EARLY_INIT_R
 
 /* Peripheral Bus Mapping */
 #define PER_PLD_ADDR		0xF4000000 /* smallest window is 1MByte 0x10 0000*/
@@ -334,7 +341,6 @@
 #define CONFIG_PHY_ADDR		1	/* PHY address			*/
 #define CONFIG_PHY_RESET_DELAY	300	/* Intel LXT971A needs this */
 #define CONFIG_PHY_CMD_DELAY	40	/* Intel LXT971A needs this */
-#define CONFIG_NET_MULTI
 /************************************************************
  * RTC
  ***********************************************************/