X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8313ERDB.h;h=863c9b9ec01bd27a6c1356befb4d5a0b56451892;hb=d060b00eff2124ad841d72aff47de5d516ead242;hp=b2af4f9823b4d1080b55b42e123a8dc3bfa3b2ac;hpb=72cd4087c9644812b0fff9440e88e986d259bf41;p=u-boot

diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index b2af4f9823..863c9b9ec0 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -82,7 +82,8 @@
 
 #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
 
-#define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_R		/* call board_early_init_r */
 
 #define CONFIG_SYS_IMMR		0xE0000000
 
@@ -130,8 +131,9 @@
  * seem to have the SPD connected to I2C.
  */
 #define CONFIG_SYS_DDR_SIZE	128		/* MB */
-#define CONFIG_SYS_DDR_CONFIG	(CSCONFIG_EN \
-				| 0x00010000	/* TODO */ \
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+				| CSCONFIG_ODT_RD_NEVER \
+				| CSCONFIG_ODT_WR_ONLY_CURRENT \
 				| CSCONFIG_ROW_BIT_13 \
 				| CSCONFIG_COL_BIT_10)
 				/* 0x80010102 */
@@ -169,12 +171,13 @@
 #if defined(CONFIG_DDR_2T_TIMING)
 #define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
-				| SDRAM_CFG_2T_EN \
-				| SDRAM_CFG_DBW_32)
+				| SDRAM_CFG_DBW_32 \
+				| SDRAM_CFG_2T_EN)
+				/* 0x43088000 */
 #else
 #define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
-				| SDRAM_CFG_32_BE)
+				| SDRAM_CFG_DBW_32)
 				/* 0x43080000 */
 #endif
 #define CONFIG_SYS_SDRAM_CFG2		0x00401000
@@ -203,9 +206,10 @@
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* buffer up multiple bytes */
 
 #define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE \
-				| (2 << BR_PS_SHIFT)	/* 16 bit port */ \
-				| BR_V)			/* valid */
-#define CONFIG_SYS_NOR_OR_PRELIM	(0xFF800000	/* 8 MByte */ \
+					| BR_PS_16	/* 16 bit port */ \
+					| BR_MS_GPCM	/* MSEL = GPCM */ \
+					| BR_V)		/* valid */
+#define CONFIG_SYS_NOR_OR_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 				| OR_GPCM_XACS \
 				| OR_GPCM_SCY_9 \
 				| OR_GPCM_EHTR \
@@ -213,7 +217,8 @@
 				/* 0xFF006FF7	TODO SLOW 16 MB flash size */
 					/* window base at flash base */
 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000017	/* 16 MB window size */
+					/* 16 MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_16MB)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	135	/* sectors per device */
@@ -262,21 +267,23 @@
 #define CONFIG_CMD_MTDPARTS
 #define MTDIDS_DEFAULT			"nand0=e2800000.flash"
 #define MTDPARTS_DEFAULT		\
-	"mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
+	"mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
 
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_CMD_NAND 1
 #define CONFIG_NAND_FSL_ELBC 1
 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 
 
 #define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
-				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
 				| BR_PS_8		/* 8 bit port */ \
 				| BR_MS_FCM		/* MSEL = FCM */ \
 				| BR_V)			/* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM	(0xFFFF8000	/* length 32K */ \
+#define CONFIG_SYS_NAND_OR_PRELIM	\
+				(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
 				| OR_FCM_CSCT \
 				| OR_FCM_CST \
 				| OR_FCM_CHT \
@@ -298,31 +305,57 @@
 #endif
 
 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
 
 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 
-/* local bus read write buffer mapping */
-#define CONFIG_SYS_BR3_PRELIM		0xFA000801	/* map at 0xFA000000 */
-#define CONFIG_SYS_OR3_PRELIM		0xFFFF8FF7	/* 32kB */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM	0xFA000000
-#define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
+/* local bus write LED / read status buffer (BCSR) mapping */
+#define CONFIG_SYS_BCSR_ADDR		0xFA000000
+#define CONFIG_SYS_BCSR_SIZE		(32 * 1024)	/* 0x00008000 */
+					/* map at 0xFA000000 on LCS3 */
+#define CONFIG_SYS_BR3_PRELIM		(CONFIG_SYS_BCSR_ADDR \
+					| BR_PS_8	/* 8 bit port */ \
+					| BR_MS_GPCM	/* MSEL = GPCM */ \
+					| BR_V)		/* valid */
+					/* 0xFA000801 */
+#define CONFIG_SYS_OR3_PRELIM		(P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
+					| OR_GPCM_CSNT \
+					| OR_GPCM_ACS_DIV2 \
+					| OR_GPCM_XACS \
+					| OR_GPCM_SCY_15 \
+					| OR_GPCM_TRLX_SET \
+					| OR_GPCM_EHTR_SET \
+					| OR_GPCM_EAD)
+					/* 0xFFFF8FF7 */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_BCSR_ADDR
+#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
 
 /* Vitesse 7385 */
 
-#define CONFIG_SYS_VSC7385_BASE	0xF0000000
-
 #ifdef CONFIG_VSC7385_ENET
 
-					/* VSC7385 Base address */
-#define CONFIG_SYS_BR2_PRELIM		0xf0000801
-					/* VSC7385, 128K bytes*/
-#define CONFIG_SYS_OR2_PRELIM		0xfffe09ff
+					/* VSC7385 Base address on LCS2 */
+#define CONFIG_SYS_VSC7385_BASE		0xF0000000
+#define CONFIG_SYS_VSC7385_SIZE		(128 * 1024)	/* 0x00020000 */
+
+#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_VSC7385_BASE \
+					| BR_PS_8	/* 8 bit port */ \
+					| BR_MS_GPCM	/* MSEL = GPCM */ \
+					| BR_V)		/* valid */
+#define CONFIG_SYS_OR2_PRELIM		(P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
+					| OR_GPCM_CSNT \
+					| OR_GPCM_XACS \
+					| OR_GPCM_SCY_15 \
+					| OR_GPCM_SETA \
+					| OR_GPCM_TRLX_SET \
+					| OR_GPCM_EHTR_SET \
+					| OR_GPCM_EAD)
+					/* 0xFFFE09FF */
+
 					/* Access window base at VSC7385 base */
 #define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE
-					/* Access window size 128K */
-#define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000010
+#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
 
 #endif
 
@@ -331,6 +364,9 @@
 #define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
+#define CONFIG_MPC83XX_GPIO 1
+#define CONFIG_CMD_GPIO 1
+
 /*
  * Serial Port
  */
@@ -549,7 +585,8 @@
 
 /* System IO Config */
 #define CONFIG_SYS_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2)	/* RGMII */
-#define CONFIG_SYS_SICRL	SICRL_USBDR_10	/* Enable Internal USB Phy  */
+			/* Enable Internal USB Phy and GPIO on LCD Connector */
+#define CONFIG_SYS_SICRL	(SICRL_USBDR_10 | SICRL_LBC)
 
 #define CONFIG_SYS_HID0_INIT	0x000000000
 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \