X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8323ERDB.h;h=e25d5acc13641907f03ec372f678470ccfc68ee7;hb=95e39793312ab1ce01615f2b5330382e99ed6e81;hp=c6ac91a536c37e3bf966e7564befb99ea2942fa7;hpb=f61f1e150c84f5b9347fca79a4bc5f2286c545d2;p=u-boot diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index c6ac91a536..e25d5acc13 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -14,11 +14,12 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83XX 1 /* MPC83xx family */ -#define CONFIG_MPC832X 1 /* MPC832x CPU specific */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC832x 1 /* MPC832x CPU specific */ + +#define CONFIG_SYS_TEXT_BASE 0xFE000000 #define CONFIG_PCI 1 -#define CONFIG_83XX_GENERIC_PCI 1 /* * System Clock Setup @@ -147,7 +148,7 @@ /* * The reserved memory */ -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) #define CONFIG_SYS_RAMBOOT @@ -156,7 +157,7 @@ #endif /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* @@ -164,14 +165,14 @@ */ #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* @@ -248,34 +249,8 @@ #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ -/* - * LSDMR masks - */ -#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - #define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723 -/* - * SDRAM Controller configuration sequence. - */ -#define CONFIG_SYS_LBC_LSDMR_1 ( CONFIG_SYS_LBC_LSDMR_COMMON \ - | CONFIG_SYS_LBC_LSDMR_OP_PCHALL) -#define CONFIG_SYS_LBC_LSDMR_2 ( CONFIG_SYS_LBC_LSDMR_COMMON \ - | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_3 ( CONFIG_SYS_LBC_LSDMR_COMMON \ - | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_4 ( CONFIG_SYS_LBC_LSDMR_COMMON \ - | CONFIG_SYS_LBC_LSDMR_OP_MRW) -#define CONFIG_SYS_LBC_LSDMR_5 ( CONFIG_SYS_LBC_LSDMR_COMMON \ - | CONFIG_SYS_LBC_LSDMR_OP_NORMAL) - #endif /* @@ -288,7 +263,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -301,6 +275,7 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ /* Use the HUSH parser */ #define CONFIG_SYS_HUSH_PARSER #ifdef CONFIG_SYS_HUSH_PARSER @@ -363,7 +338,7 @@ * QE UEC ethernet configuration */ #define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "FSL UEC0" +#define CONFIG_ETHPRIME "UEC0" #define CONFIG_UEC_ETH1 /* ETH3 */ @@ -373,7 +348,8 @@ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 4 -#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_MII +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 #endif #define CONFIG_UEC_ETH2 /* ETH4 */ @@ -384,7 +360,8 @@ #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 0 -#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_MII +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 #endif /* @@ -427,7 +404,7 @@ #define CONFIG_CMD_PCI #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif @@ -453,16 +430,17 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE /* @@ -530,14 +508,6 @@ #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - #if (CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ @@ -549,17 +519,11 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */ -#define CONFIG_ETHADDR 00:04:9f:ef:03:01 #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ -#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */ #define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00 /* MAC address offset in I2C EEPROM */ -#define CONFIG_IPADDR 10.0.0.2 -#define CONFIG_SERVERIP 10.0.0.1 -#define CONFIG_GATEWAYIP 10.0.0.1 -#define CONFIG_NETMASK 255.0.0.0 #define CONFIG_NETDEV eth1 #define CONFIG_HOSTNAME mpc8323erdb @@ -569,7 +533,7 @@ #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #define CONFIG_FDTFILE mpc832x_rdb.dtb -#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 @@ -580,12 +544,12 @@ "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftp $loadaddr $uboot;" \ - "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ - "fdtaddr=400000\0" \ + "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ + "fdtaddr=780000\0" \ "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ "ramdiskaddr=1000000\0" \ "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \