X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC832XEMDS.h;h=18418e398e53bc0022771a495110556d669ad5df;hb=744368d6ae3ea5cf73407c24d8e44b2a83b7f659;hp=40a1e0ee1ef89695e96849361bc83af6a112476c;hpb=72cd4087c9644812b0fff9440e88e986d259bf41;p=u-boot diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 40a1e0ee1e..18418e398e 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -1,31 +1,19 @@ /* * Copyright (C) 2006 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_DISPLAY_BOARDINFO + /* * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ @@ -111,17 +99,53 @@ /* Manually set up DDR parameters */ #define CONFIG_SYS_DDR_SIZE 128 /* MB */ -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80840102 -#define CONFIG_SYS_DDR_TIMING_0 0x00220802 -#define CONFIG_SYS_DDR_TIMING_1 0x3935d322 -#define CONFIG_SYS_DDR_TIMING_2 0x0f9048ca +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_AP \ + | CSCONFIG_ODT_WR_CFG \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) + /* 0x80840102 */ +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00220802 */ +#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (5 << TIMING_CFG1_CASLAT_SHIFT) \ + | (13 << TIMING_CFG1_REFREC_SHIFT) \ + | (3 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x3935D322 */ +#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (31 << TIMING_CFG2_CPO_SHIFT) \ + | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (10 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x0F9048CA */ #define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 -#define CONFIG_SYS_DDR_MODE 0x44400232 +#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + /* 0x02000000 */ +#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0232 << SDRAM_MODE_SD_SHIFT)) + /* 0x44400232 */ #define CONFIG_SYS_DDR_MODE2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x03200064 +#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x03200064 */ #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080000 +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_32_BE) + /* 0x43080000 */ #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 #endif @@ -144,8 +168,8 @@ #endif /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* * Initial RAM Base Address Setup @@ -174,12 +198,22 @@ /* Window base at flash base */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | (2 << BR_PS_SHIFT) /* 16 bit port */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xfe006ff7 */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ @@ -192,100 +226,72 @@ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR - /* Access window size 32K */ -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E - - /* Port size=8bit, MSEL=GPCM */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) -#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ - -/* - * SDRAM on the Local Bus - */ -#undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */ - -#ifdef CONFIG_SYS_LB_SDRAM -#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ - -/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into - * the top 17 bits of BR2. - */ - -#define CONFIG_SYS_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CONFIG_SYS_OR2_PRELIM 0xfc006901 - - /* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_LSRT 0x32000000 - /* LB refresh timer prescal, 266MHz/32 */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723 - -#endif +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ + | BR_PS_8 \ + | BR_MS_GPCM \ + | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xFFFFE9F7 */ /* * Windows to access PIB via local bus */ - /* windows base 0xf8008000 */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000 - /* windows size 64KB */ -#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f + /* PIB window base 0xF8008000 */ +#define CONFIG_SYS_PIB_BASE 0xF8008000 +#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024) +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) /* * CS2 on Local Bus, to PIB */ - /* CS2 base address at 0xf8008000 */ -#define CONFIG_SYS_BR2_PRELIM 0xf8008801 - /* size 32KB, port size 8bit, GPCM */ -#define CONFIG_SYS_OR2_PRELIM 0xffffe9f7 +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \ + | BR_PS_8 \ + | BR_MS_GPCM \ + | BR_V) + /* 0xF8008801 */ +#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xffffe9f7 */ /* * CS3 on Local Bus, to PIB */ - /* CS3 base address at 0xf8010000 */ -#define CONFIG_SYS_BR3_PRELIM 0xf8010801 - /* size 32KB, port size 8bit, GPCM */ -#define CONFIG_SYS_OR3_PRELIM 0xffffe9f7 +#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \ + CONFIG_SYS_PIB_WINDOW_SIZE) \ + | BR_PS_8 \ + | BR_MS_GPCM \ + | BR_V) + /* 0xF8010801 */ +#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xffffe9f7 */ /* * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -298,25 +304,14 @@ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_FSL_I2C -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } /* * Config on-board RTC @@ -342,8 +337,8 @@ #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 - #ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_83XX_PCI_STREAMING @@ -411,26 +406,14 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_ASKENV #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI #endif -#if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_SAVEENV - #undef CONFIG_CMD_LOADS -#endif - - #undef CONFIG_WATCHDOG /* watchdog disabled */ /* @@ -438,7 +421,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -451,7 +433,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -460,6 +441,7 @@ */ /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Core HID Setup @@ -573,7 +555,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -589,7 +570,6 @@ #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -619,7 +599,6 @@ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" - #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND #endif /* __CONFIG_H */