X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8536DS.h;h=e379d5327d9acbb709045312bc98567cf4f4f16e;hb=6b7243aa89cdacefe46963dbe11cee0cbf021a49;hp=c4389cc44654deb41edc8e65385db72222bcd261;hpb=f8030519bbe20b836f3939742b959cbadfaad51b;p=u-boot

diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index c4389cc446..e379d5327d 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -34,6 +34,7 @@
 #define CONFIG_MPC8536		1
 #define CONFIG_MPC8536DS	1
 
+#define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCI1		1	/* Enable PCI controller 1 */
 #define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
@@ -70,7 +71,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 
 #define CONFIG_ENABLE_36BIT_PHYS	1
 
@@ -99,7 +99,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_DDR_SPD
 #undef CONFIG_DDR_DLL
 
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
@@ -155,8 +155,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
  *
  * Localbus non-cacheable
- * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
+ * 0xe000_0000	0xe7ff_ffff	Promjet/free		128M non-cacheable
  * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
+ * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
  * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
@@ -166,12 +167,13 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Local Bus Definitions
  */
 #define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 
-#define CONFIG_SYS_BR0_PRELIM		0xe8001001
-#define CONFIG_SYS_OR0_PRELIM		0xf8000ff7
+#define CONFIG_SYS_BR0_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR0_PRELIM	0xf8000ff7
 
-#define CONFIG_SYS_BR1_PRELIM		0xe0001001
-#define CONFIG_SYS_OR1_PRELIM		0xf8000ff7
+#define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
 
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE}
 #define CONFIG_SYS_FLASH_QUIET_TEST
@@ -194,8 +196,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 
 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
 #define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
+#define PIXIS_BASE_PHYS	PIXIS_BASE
 
-#define CONFIG_SYS_BR3_PRELIM	(PIXIS_BASE | 0x0801)	/* port size 8bit */
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 #define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
 
 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
@@ -230,8 +233,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
 #define CONFIG_SYS_PIXIS_VBOOT_MASK	0xc0
 
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */
@@ -243,6 +244,56 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
 
+#define CONFIG_SYS_NAND_BASE           0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS      CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
+				CONFIG_SYS_NAND_BASE + 0x40000, \
+				CONFIG_SYS_NAND_BASE + 0x80000, \
+				CONFIG_SYS_NAND_BASE + 0xC0000}
+#define CONFIG_SYS_MAX_NAND_DEVICE	4
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND		1
+#define CONFIG_NAND_FSL_ELBC	1
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8              /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CONFIG_NAND_OR_PRELIM	(0xFFFC0000            /* length 256K */ \
+				| OR_FCM_PGS            /* Large Page*/ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
+
+#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8              /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CONFIG_SYS_OR4_PRELIM	CONFIG_NAND_OR_PRELIM     /* NAND Options */
+#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8              /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CONFIG_SYS_OR5_PRELIM	CONFIG_NAND_OR_PRELIM     /* NAND Options */
+
+#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8              /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CONFIG_SYS_OR6_PRELIM	CONFIG_NAND_OR_PRELIM     /* NAND Options */
+
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
@@ -307,34 +358,42 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI1_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS	0xffc00000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_BASE	0x90000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x90000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x90000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x90000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x08000000	/* 128M */
-#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc10000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_BASE	0x98000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0x98000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0x98000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0x98000000
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x08000000	/* 128M */
-#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc20000
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
-#define CONFIG_SYS_PCIE3_MEM_BASE	0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	CONFIG_SYS_PCIE3_MEM_BASE
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xa0000000
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE3_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc30000
+#define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xffc30000
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 
@@ -344,10 +403,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
 /*PCIE video card used*/
-#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE3_IO_PHYS
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE3_IO_VIRT
 
 /*PCI video card used*/
-/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_PHYS*/
+/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_VIRT*/
 
 /* video */
 #define CONFIG_VIDEO
@@ -360,7 +419,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_ATI_RADEON_FB
 #define CONFIG_VIDEO_LOGO
 /*#define CONFIG_CONSOLE_CURSOR*/
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_PHYS
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
 #endif
 
 #undef CONFIG_EEPRO100
@@ -374,8 +433,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #endif
 
 #ifndef CONFIG_PCI_PNP
-	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BASE
-	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_IO_BASE
+	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BUS
+	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_IO_BUS
 	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
 #endif
 
@@ -440,7 +499,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 #define CONFIG_ENV_ADDR		0xfff80000
 #else
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x60000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #endif
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */