X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8541CDS.h;h=5f12eeecc518e7d7eef4465baeffadf68992688f;hb=2fd90ce575b02d189cbf443c85309bcd001aa393;hp=c96b98b54d3c3da837e729288763bce1496edc14;hpb=b4f15fdaf77b7339e2984703c83269c7cdf680a9;p=u-boot diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index c96b98b54d..5f12eeecc5 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -308,47 +308,58 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8541@0" +#define OF_SOC "soc8541@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600" + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI) +#define CONFIG_MPC85XX_PCI2 #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ @@ -362,10 +373,10 @@ extern unsigned long get_clock_freq(void); #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 @@ -390,19 +401,19 @@ extern unsigned long get_clock_freq(void); #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII + #if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) + #define CONFIG_CMD_PCI #endif -#include + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -412,7 +423,7 @@ extern unsigned long get_clock_freq(void); #define CFG_LONGHELP /* undef to save memory */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -432,7 +443,7 @@ extern unsigned long get_clock_freq(void); /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif @@ -444,7 +455,7 @@ extern unsigned long get_clock_freq(void); #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -482,8 +493,10 @@ extern unsigned long get_clock_freq(void); #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -491,7 +504,8 @@ extern unsigned long get_clock_freq(void); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \