X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8541CDS.h;h=a64565db931f5c2ecda6647c2f48361415ea6d6c;hb=3070a9a3cb41ed6b19f79590f7713d5685ab1066;hp=d2e7237895e29acbd2850e0cc45b7dd91c54ba33;hpb=82ac8c97145a4c3bf8b3dbfad00fa96e920f9b9c;p=u-boot

diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index d2e7237895..a64565db93 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -38,7 +38,7 @@
 #define CONFIG_MPC8541CDS	1	/* MPC8541CDS board specific */
 
 #define CONFIG_PCI
-#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
@@ -47,6 +47,10 @@
 #define CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+#define CONFIG_FSL_VIA
+#define CONFIG_FSL_CDS_EEPROM
 
 /*
  * When initializing flash, if we cannot find the manufacturer ID,
@@ -65,13 +69,10 @@ extern unsigned long get_clock_freq(void);
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
-#define CONFIG_L2_CACHE		    	    /* toggle L2 cache 	*/
+#define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
 #define CONFIG_BTB			    /* toggle branch predition */
 #define CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
 
-#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
-
-#undef	CFG_DRAM_TEST			/* memory test, takes time */
 #define CFG_MEMTEST_START	0x00200000	/* memtest works on */
 #define CFG_MEMTEST_END		0x00400000
 
@@ -79,8 +80,9 @@ extern unsigned long get_clock_freq(void);
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 /*
@@ -150,7 +152,7 @@ extern unsigned long get_clock_freq(void);
 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #define CFG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
@@ -272,21 +274,23 @@ extern unsigned long get_clock_freq(void);
  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  */
 
+#define CONFIG_FSL_CADMUS
+
 #define CADMUS_BASE_ADDR 0xf8000000
 #define CFG_BR3_PRELIM   0xf8000801
 #define CFG_OR3_PRELIM   0xfff00ff7
 
 #define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_LOCK	1
 #define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CFG_INIT_RAM_END    	0x4000	    /* End of used area in RAM */
+#define CFG_INIT_RAM_END	0x4000	    /* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE  	128	    /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	128	    /* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    	(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN	    	(128 * 1024)	/* Reserved for malloc */
+#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     2
@@ -355,7 +359,7 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_MPC85XX_PCI2
 #define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
@@ -369,7 +373,7 @@ extern unsigned long get_clock_freq(void);
 #if defined(CONFIG_TSEC_ENET)
 
 #ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 	1
+#define CONFIG_NET_MULTI	1
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
@@ -448,14 +452,7 @@ extern unsigned long get_clock_freq(void);
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux*/
-
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE	32768
-#define CFG_CACHELINE_SIZE	32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
-#endif
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions