X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8544DS.h;h=dade6d3b89cd18556c77adebec6597a73f3def3b;hb=09424d11192cffd4793b7bc922c5b47d4fe88a4d;hp=0987448b71643e6834d622902ce3c5740163ade4;hpb=50bd0057ba8fceeb48533f8b1a652ccd0e170838;p=u-boot diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 0987448b71..dade6d3b89 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -1,23 +1,7 @@ /* - * Copyright 2007 Freescale Semiconductor, Inc. + * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -30,31 +14,30 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8544 1 #define CONFIG_MPC8544DS 1 +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xfff80000 +#endif + #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI1 1 /* PCI controller 1 */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ -/* - * When initializing flash, if we cannot find the manufacturer ID, - * assume this is the AMD flash associated with the CDS board. - * This allows booting from a promjet. - */ -#define CONFIG_ASSUME_AMD_FLASH - #ifndef __ASSEMBLY__ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif @@ -65,7 +48,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ /* * Only possible on E500 Version 2 or newer cores. @@ -76,27 +58,16 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_PANIC_HANG /* do not reset board on panic */ -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ - -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000) +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD -#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 @@ -165,7 +136,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI @@ -192,6 +163,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ +#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ +#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ @@ -206,15 +179,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ @@ -225,7 +195,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -239,81 +208,83 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* Use the HUSH parser */ #define CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 -#define CONFIG_SYS_64BIT_STRTOUL 1 -#define CONFIG_SYS_64BIT_VSPRINTF 1 - /* I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3100 /* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ +#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ -#define CONFIG_SYS_PCI1_MEM_BASE 0xc0000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ -/* PCI view of System Memory */ -#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000 - /* controller 2, Slot 1, tgtid 1, Base address 9000 */ -#define CONFIG_SYS_PCIE2_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE +#define CONFIG_SYS_PCIE2_NAME "Slot 1" +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 2,tgtid 2, Base address a000 */ -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_NAME "Slot 2" +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 3, direct to uli, tgtid 3, Base address b000 */ -#define CONFIG_SYS_PCIE3_MEM_BASE 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE +#define CONFIG_SYS_PCIE3_NAME "ULI" +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ -#define CONFIG_SYS_PCIE3_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ -#define CONFIG_SYS_PCIE3_MEM_BASE2 0xb0200000 -#define CONFIG_SYS_PCIE3_MEM_PHYS2 CONFIG_SYS_PCIE3_MEM_BASE2 +#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 +#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 +#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ #if defined(CONFIG_PCI) /*PCIE video card used*/ -#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_PHYS +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT /*PCI video card used*/ -/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/ +/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ /* video */ #define CONFIG_VIDEO @@ -329,22 +300,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET #endif -#define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP #define CONFIG_RTL8139 -#ifdef CONFIG_RTL8139 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) -#define _IO_BASE 0x00000000 -#endif - #ifndef CONFIG_PCI_PNP - #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BASE + #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS + #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ #endif @@ -353,6 +317,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SCSI_AHCI #ifdef CONFIG_SCSI_AHCI +#define CONFIG_LIBATA #define CONFIG_SATA_ULI5288 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 #define CONFIG_SYS_SCSI_MAX_LUN 1 @@ -365,10 +330,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if defined(CONFIG_TSEC_ENET) -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ #define CONFIG_TSEC1 1 @@ -429,15 +390,27 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI - #define CONFIG_CMD_BEDBUG #define CONFIG_CMD_NET #define CONFIG_CMD_SCSI #define CONFIG_CMD_EXT2 #endif +/* + * USB + */ +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI_PCI +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_STORAGE +#define CONFIG_PCI_EHCI_DEVICE 0 +#endif #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -445,9 +418,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -456,26 +429,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -493,8 +457,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_IPADDR 192.168.1.251 #define CONFIG_HOSTNAME 8544ds_unknown -#define CONFIG_ROOTPATH /nfs/mpc85xx -#define CONFIG_BOOTFILE 8544ds/uImage.uboot +#define CONFIG_ROOTPATH "/nfs/mpc85xx" +#define CONFIG_BOOTFILE "8544ds/uImage.uboot" #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ #define CONFIG_SERVERIP 192.168.1.1 @@ -509,20 +473,25 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=8544ds/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ - "fdtfile=8544ds/mpc8544ds.dtb\0" \ - "bdev=sda3\0" +"netdev=eth0\0" \ +"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ +"tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize\0" \ +"consoledev=ttyS0\0" \ +"ramdiskaddr=2000000\0" \ +"ramdiskfile=8544ds/ramdisk.uboot\0" \ +"fdtaddr=c00000\0" \ +"fdtfile=8544ds/mpc8544ds.dtb\0" \ +"bdev=sda3\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \