X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8568MDS.h;h=21735e5e52a3c744a1bd84b21fb9301e1f307de2;hb=c960ef29cd1bffccb84366cc6ca9c290cb3c36a0;hp=281918bdc9ec7c1e6061bf2a90380f05f3d79230;hpb=25ddd1fb0a2281b182529afbc8fda5de2dc16d96;p=u-boot diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 281918bdc9..21735e5e52 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -1,23 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2004-2007 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. */ /* @@ -26,25 +9,17 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ -#define CONFIG_MPC8568 1 /* MPC8568 specific */ -#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ - -#define CONFIG_SYS_TEXT_BASE 0xfff80000 +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI1 1 /* PCI controller */ #define CONFIG_PCIE1 1 /* PCIE controller */ #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_QE /* Enable QE */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #ifndef __ASSEMBLY__ extern unsigned long get_clock_freq(void); @@ -62,27 +37,16 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_ENABLE_36BIT_PHYS 1 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD -#define CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef @@ -90,7 +54,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) @@ -162,14 +125,12 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO - /* * SDRAM on the LocalBus */ #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - /*Chip select 2 - SDRAM*/ #define CONFIG_SYS_BR2_PRELIM 0xf0001861 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 @@ -241,11 +202,9 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* Serial Port */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -256,30 +215,19 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) -/* Use the HUSH parser*/ -#define CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 /* * General PCI @@ -294,6 +242,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ +#define CONFIG_SYS_PCIE1_NAME "Slot" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 @@ -303,9 +252,10 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ -#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 -#define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ #ifdef CONFIG_QE /* @@ -330,7 +280,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 7 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 #endif @@ -342,16 +292,12 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 #endif #endif /* CONFIG_QE */ #if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -360,10 +306,6 @@ extern unsigned long get_clock_freq(void); #endif /* CONFIG_PCI */ -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - #if defined(CONFIG_TSEC_ENET) #define CONFIG_MII 1 /* MII PHY management */ @@ -389,72 +331,35 @@ extern unsigned long get_clock_freq(void); /* * Environment */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - /* * BOOTP options */ #define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_SETEXPR -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - #undef CONFIG_WATCHDOG /* watchdog disabled */ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -464,20 +369,16 @@ extern unsigned long get_clock_freq(void); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) #define CONFIG_HAS_ETH0 -#define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD #define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD #define CONFIG_HAS_ETH3 -#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif #define CONFIG_IPADDR 192.168.1.253 -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage +#define CONFIG_HOSTNAME "unknown" +#define CONFIG_ROOTPATH "/nfsroot" +#define CONFIG_BOOTFILE "your.uImage" #define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1 @@ -485,11 +386,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ - -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ @@ -504,14 +400,12 @@ extern unsigned long get_clock_freq(void); "ramargs=setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs\0" \ - #define CONFIG_NFSBOOTCOMMAND \ "run nfsargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" - #define CONFIG_RAMBOOTCOMMAND \ "run ramargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \