X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC885ADS.h;h=eeb2355b9f0abd671978f738c8eb49efaf6298a2;hb=1c1b7c3739095da7d73fef3adbe9f187791ca9ff;hp=74318e55456f6e8a19f02f295cf66c6ac4c595fc;hpb=038ccac511214b062c56f22b9413f784b86bcd87;p=u-boot diff --git a/include/configs/MPC885ADS.h b/include/configs/MPC885ADS.h index 74318e5545..eeb2355b9f 100644 --- a/include/configs/MPC885ADS.h +++ b/include/configs/MPC885ADS.h @@ -1,46 +1,38 @@ /* * A collection of structures, addresses, and values associated with - * the Motorola DUET ADS board. Values common to all FADS family boards + * the Motorola MPC885ADS board. Values common to all FADS family boards * are in board/fads/fads.h * - * Copyright (C) 2003 Arabella Software Ltd. + * Copyright (C) 2003-2004 Arabella Software Ltd. * Yuli Barcohen */ #ifndef __CONFIG_H #define __CONFIG_H -/* Board type */ -#define CONFIG_MPC885ADS 1 /* Duet (MPC87x/88x) ADS */ +#define CONFIG_MPC885ADS 1 /* MPC885ADS board */ #define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ -#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */ +#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */ -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#define CONFIG_SYS_TEXT_BASE 0xFE000000 + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 38400 -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ - -#define CFG_PLPRCR ((1 << PLPRCR_MFD_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS) +#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ +#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 +#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000 +#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 #define CONFIG_SDRAM_50MHZ 1 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) - -#include "fads.h" - -#undef CFG_SCCR -#define CFG_SCCR (SCCR_TBS|SCCR_EBDF11) +#include "../../board/fads/fads.h" -#define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ -#define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ +#define CONFIG_SYS_BR5_PRELIM (CONFIG_SYS_PHYDEV_ADDR | BR_PS_8 | BR_V) #define CONFIG_HAS_ETH1