X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FP1010RDB.h;h=57aef21e96c9d4de5fe3337340454a700f1bbfd7;hb=b7e3129e550957f046c29a917c63f4b503fbfcb9;hp=ff35fb17808e7875185b48f5cf3392bc301d127f;hpb=d793e5a840b417e9c168110deb58572e7ee586cb;p=u-boot

diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index ff35fb1780..57aef21e96 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -59,6 +59,13 @@
 #endif /* CONFIG_NAND_SPL */
 #endif
 
+
+#ifdef CONFIG_NAND_SECBOOT	/* NAND Boot */
+#define CONFIG_RAMBOOT_NAND
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#endif
+
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE		0xeff80000
 #endif
@@ -174,7 +181,7 @@
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR3
-#define CONFIG_DDR_RAW_TIMING
+#define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM		1
 #define SPD_EEPROM_ADDRESS		0x52
@@ -345,7 +352,7 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_NAND_DDR_LAW		11
 
 /* Set up IFC registers for boot location NOR/NAND */
-#ifdef CONFIG_NAND_U_BOOT
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SECBOOT)
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
@@ -446,7 +453,6 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_NS16550_MIN_FUNCTIONS
 #endif
 
-#define CONFIG_SERIAL_MULTI		/* Enable both serial ports */
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
 
 #define CONFIG_SYS_BAUDRATE_TABLE	\
@@ -457,9 +463,6 @@ extern unsigned long get_sdram_size(void);
 
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
-#ifdef	CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
 
 /*
  * Pass open firmware flat tree
@@ -501,7 +504,7 @@ extern unsigned long get_sdram_size(void);
  * SPI interface will not be available in case of NAND boot SPI CS0 will be
  * used for SLIC
  */
-#ifndef CONFIG_NAND_U_BOOT
+#if !defined(CONFIG_NAND_U_BOOT) || !defined(CONFIG_NAND_SECBOOT)
 /* eSPI - Enhanced SPI */
 #define CONFIG_FSL_ESPI
 #define CONFIG_SPI_FLASH
@@ -512,10 +515,6 @@ extern unsigned long get_sdram_size(void);
 #endif
 
 #if defined(CONFIG_TSEC_ENET)
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI
-#endif
-
 #define CONFIG_MII			/* MII PHY management */
 #define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
 #define CONFIG_TSEC1	1
@@ -602,6 +601,7 @@ extern unsigned long get_sdram_size(void);
 #if defined(CONFIG_SYS_RAMBOOT)
 #if defined(CONFIG_RAMBOOT_SDCARD)
 #define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_FSL_FIXED_MMC_LOCATION
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_ENV_SIZE			0x2000
 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
@@ -712,8 +712,8 @@ extern unsigned long get_sdram_size(void);
 #endif
 
 #define CONFIG_HOSTNAME		P1010RDB
-#define CONFIG_ROOTPATH		/opt/nfsroot
-#define CONFIG_BOOTFILE		uImage
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	u-boot.bin/* U-Boot image on TFTP server */
 
 /* default location for tftp and bootm */
@@ -725,9 +725,9 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_BAUDRATE		115200
 
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
-	"hwconfig=" MK_STR(CONFIG_DEF_HWCONFIG)  "\0"	\
+	"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"	\
 	"netdev=eth0\0"						\
-	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
 	"loadaddr=1000000\0"			\
 	"consoledev=ttyS0\0"				\
 	"ramdiskaddr=2000000\0"			\
@@ -762,4 +762,8 @@ extern unsigned long get_sdram_size(void);
 
 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
 #endif	/* __CONFIG_H */