X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FP1010RDB.h;h=78e006492da3f250df083b7db9fe393fa23fea9e;hb=05cb79a72cc3b99a0238e8b8eeec6d3ffd8b0674;hp=3c0faca1347d8e02d0f72ece2bed9f5deb0cd27e;hpb=cd85bec36d0e0d16fedb00e0c434ed070a9c6b37;p=u-boot diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 3c0faca134..78e006492d 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -11,29 +11,14 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifdef CONFIG_36BIT -#define CONFIG_PHYS_64BIT -#endif -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_P1010 #define CONFIG_E500 /* BOOKE e500 family */ #include #define CONFIG_NAND_FSL_IFC #ifdef CONFIG_SDCARD -#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT -#define CONFIG_SPL_DRIVERS_MISC_SUPPORT -#define CONFIG_SPL_ENV_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_MMC_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x11001000 #define CONFIG_SPL_TEXT_BASE 0xD0001000 #define CONFIG_SPL_PAD_TO 0x18000 @@ -56,19 +41,9 @@ #define CONFIG_SYS_TEXT_BASE 0x11000000 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #else -#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT -#define CONFIG_SPL_DRIVERS_MISC_SUPPORT -#define CONFIG_SPL_ENV_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_SPI_SUPPORT -#define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x11001000 #define CONFIG_SPL_TEXT_BASE 0xD0001000 #define CONFIG_SPL_PAD_TO 0x18000 @@ -89,8 +64,6 @@ #ifdef CONFIG_NAND #ifdef CONFIG_SECURE_BOOT #define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_BOOT #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" @@ -109,15 +82,7 @@ #ifdef CONFIG_TPL_BUILD #define CONFIG_SPL_NAND_BOOT #define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SPL_NAND_INIT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_DRIVERS_MISC_SUPPORT -#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT #define CONFIG_SPL_COMMON_INIT_DDR #define CONFIG_SPL_MAX_SIZE (128 << 10) #define CONFIG_SPL_TEXT_BASE 0xD0001000 @@ -128,8 +93,6 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) #elif defined(CONFIG_SPL_BUILD) #define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TEXT_BASE 0xff800000 @@ -174,10 +137,9 @@ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ -#define CONFIG_PCI /* Enable PCI/PCIE */ #if defined(CONFIG_PCI) -#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ @@ -185,7 +147,6 @@ #define CONFIG_CMD_PCI - /* * PCI Windows * Memory space is mapped 1-1, but I/O space must start from 0. @@ -211,9 +172,9 @@ #endif /* controller 2, Slot 2, tgtid 2, Base address 9000 */ -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" #endif #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 @@ -234,13 +195,10 @@ #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION #endif -#define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_TSEC_ENET #define CONFIG_ENV_OVERWRITE @@ -417,7 +375,7 @@ extern unsigned long get_sdram_size(void); | CSPR_V) #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ @@ -427,7 +385,7 @@ extern unsigned long get_sdram_size(void); | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ @@ -443,7 +401,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_CMD_NAND -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) /* NAND Flash Timing Params */ #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ FTIM0_NAND_TWP(0x0C) | \ @@ -458,7 +416,7 @@ extern unsigned long get_sdram_size(void); FTIM2_NAND_TWHRE(0x0f) #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ /* ONFI NAND Flash mode0 Timing Params */ #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ @@ -555,9 +513,9 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET @@ -611,28 +569,12 @@ extern unsigned long get_sdram_size(void); #define CONFIG_NS16550_MIN_FUNCTIONS #endif -#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ - #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* - * Pass open firmware flat tree - */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_OF_STDOUT_VIA_ALIAS - -/* new uImage format support */ -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ - /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_FSL @@ -647,7 +589,7 @@ extern unsigned long get_sdram_size(void); #define I2C_PCA9557_BUS_NUM 0 /* I2C EEPROM */ -#if defined(CONFIG_P1010RDB_PB) +#if defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_ID_EEPROM #ifdef CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID @@ -667,15 +609,12 @@ extern unsigned long get_sdram_size(void); #define CONFIG_RTC_PT7C4338 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_CMD_I2C - /* * SPI interface will not be available in case of NAND boot SPI CS0 will be * used for SLIC */ #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) /* eSPI - Enhanced SPI */ -#define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #endif @@ -716,7 +655,6 @@ extern unsigned long get_sdram_size(void); #endif /* CONFIG_TSEC_ENET */ - /* SATA */ #define CONFIG_FSL_SATA #define CONFIG_FSL_SATA_V2 @@ -737,7 +675,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_MMC #ifdef CONFIG_MMC -#define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION #define CONFIG_FSL_ESDHC #define CONFIG_GENERIC_MMC @@ -750,10 +687,8 @@ extern unsigned long get_sdram_size(void); #define CONFIG_USB_EHCI #ifdef CONFIG_USB_EHCI -#define CONFIG_CMD_USB #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL -#define CONFIG_USB_STORAGE #endif #endif @@ -780,10 +715,10 @@ extern unsigned long get_sdram_size(void); #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) #else -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_ENV_SIZE (16 * 1024) #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ #endif @@ -809,16 +744,12 @@ extern unsigned long get_sdram_size(void); #define CONFIG_CMD_DATE #define CONFIG_CMD_ERRATA #define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO #undef CONFIG_WATCHDOG /* watchdog disabled */ #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ || defined(CONFIG_FSL_SATA) -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION #endif @@ -846,14 +777,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - /* * For booting Linux, the board info and command line data * have to be in the first 64 MB of memory, since this is @@ -883,7 +806,6 @@ extern unsigned long get_sdram_size(void); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 @@ -896,7 +818,7 @@ extern unsigned long get_sdram_size(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=p1010rdb.dtb\0" \ "bdev=sda1\0" \ "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ @@ -917,7 +839,7 @@ extern unsigned long get_sdram_size(void); "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ CONFIG_BOOTMODE -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_BOOTMODE \ "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ @@ -926,7 +848,7 @@ extern unsigned long get_sdram_size(void); "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_BOOTMODE \ "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \