X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FP2041RDB.h;h=967c83c53bace9f8546f599e1945c80f28964dae;hb=f7d6fcf7aead384ea39bc7aba581e912c3759eaa;hp=500bb00220b3ec2f6c75f936e2ba443f6ab0bf96;hpb=ce040c83f1d74b07543fe98b07164912d104a2c7;p=u-boot diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 500bb00220..967c83c53b 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -11,8 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_P2041RDB - #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc @@ -26,13 +24,9 @@ #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_NO_FLASH #endif /* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */ @@ -45,9 +39,7 @@ #endif #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ @@ -60,11 +52,9 @@ #define CONFIG_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_DPAA_RMAN /* RMan */ -#define CONFIG_FSL_LAW /* Use common FSL init code */ - #define CONFIG_ENV_OVERWRITE -#ifdef CONFIG_SYS_NO_FLASH +#ifndef CONFIG_MTD_NOR_FLASH #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_NOWHERE #endif @@ -172,7 +162,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x52 @@ -284,7 +273,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} -#define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ #define CONFIG_MISC_INIT_R @@ -542,7 +530,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_DOS_PARTITION #endif /* CONFIG_PCI */ /* SATA */ @@ -561,8 +548,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA #define CONFIG_LBA48 -#define CONFIG_CMD_SATA -#define CONFIG_DOS_PARTITION #endif #ifdef CONFIG_FMAN_ENET @@ -594,8 +579,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* * Command line configuration. */ -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #ifdef CONFIG_PCI #define CONFIG_CMD_PCI @@ -608,25 +591,14 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_HAS_FSL_MPH_USB #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #endif -#define CONFIG_MMC - #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#define CONFIG_GENERIC_MMC -#define CONFIG_DOS_PARTITION -#endif - -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL #endif /* @@ -670,9 +642,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 - -#define CONFIG_BAUDRATE 115200 - #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \