X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FPMC405.h;h=00a12fb83339b51971e136f653582fe7b2d71a57;hb=9844d027b52cc89264f6bf7686e26d9dc50134fd;hp=c598d00cf0cec263fb1af808b0af943d6694bce1;hpb=44a01a73e8e68704fba7ce48091c70003cb4569e;p=u-boot

diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
index c598d00cf0..00a12fb833 100644
--- a/include/configs/PMC405.h
+++ b/include/configs/PMC405.h
@@ -181,6 +181,8 @@
 #define CONFIG_SYS_PCI_PTM2MS  0xff000001	/* 16MB, enable */
 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000	/* Host: use this pci address */
 
+#define CONFIG_PCI_4xx_PTM_OVERWRITE	1 /* overwrite PTMx settings by env */
+
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
@@ -233,6 +235,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		100000 /* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
@@ -282,9 +285,6 @@
 /*
  * FPGA stuff
  */
-#define CONFIG_SYS_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD */
-#define CONFIG_SYS_FPGA_MAX_SIZE	(32 * 1024) /* 32kByte for CPLD */
-
 /* FPGA program pin configuration */
 #define CONFIG_SYS_FPGA_PRG		0x04000000 /* JTAG TMS pin (output) */
 #define CONFIG_SYS_FPGA_CLK		0x02000000 /* JTAG TCK pin (output) */