X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FPPChameleonEVB.h;h=cf98324344c06cbed4f27c77cfb0393a5e2d8537;hb=48d0192fe869948fef14b460b5f0c85bca933693;hp=bb8ce43babfb021edb1c03cc91c0b17ba1e491c2;hpb=e55ca7e2624988f82d6f77ddab54246621260c8b;p=u-boot diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index bb8ce43bab..cf98324344 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -1,4 +1,7 @@ /* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, + * * (C) Copyright 2003 * DAVE Srl * @@ -43,6 +46,9 @@ * CONFIG_PPCHAMELEON_CLK_25 * CONFIG_PPCHAMELEON_CLK_33 */ +#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33)) +#define CONFIG_PPCHAMELEON_CLK_25 +#endif #if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33)) #error "* Two external frequencies (SysClk) are defined! *" @@ -74,11 +80,11 @@ #ifdef CONFIG_PPCHAMELEON_CLK_25 - #define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ +# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ #elif (defined (CONFIG_PPCHAMELEON_CLK_33)) -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ +# define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ #else -#error "* External frequency (SysClk) not defined! *" +# error "* External frequency (SysClk) not defined! *" #endif #define CONFIG_BAUDRATE 115200 @@ -89,6 +95,7 @@ /* Ethernet stuff */ #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ #define CONFIG_ETHADDR 00:50:c2:1e:af:fe +#define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -99,37 +106,63 @@ #define CONFIG_MII 1 /* MII PHY management */ #ifndef CONFIG_EXT_PHY -#define CONFIG_PHY_ADDR 0 /* EMAC0 PHY address */ -#define CONFIG_PHY1_ADDR 1 /* EMAC1 PHY address */ +#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */ +#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */ #else #define CONFIG_PHY_ADDR 2 /* PHY address */ #endif #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_NAND | \ - CFG_CMD_PCI ) + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SNTP + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ +#define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */ +#define CFG_I2C_RTC_ADDR 0x68 +#define CFG_M41T11_BASE_YEAR 1900 +/* + * SDRAM configuration (please see cpu/ppc/sdram.[ch]) + */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ +/* SDRAM timings used in datasheet */ +#define CFG_SDRAM_CL 2 +#define CFG_SDRAM_tRP 20 +#define CFG_SDRAM_tRC 65 +#define CFG_SDRAM_tRCD 20 +#undef CFG_SDRAM_tRFC + /* * Miscellaneous configurable options */ @@ -141,7 +174,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -177,34 +210,34 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ +/* + * nand device 1 on dave (PPChameleonEVB) needs more time, + * so we just introduce additional wait in nand_wait(), + * effectively for both devices. + */ +#define PPCHAMELON_NAND_TIMER_HACK + #define CFG_NAND0_BASE 0xFF400000 #define CFG_NAND1_BASE 0xFF000000 +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, CFG_NAND1_BASE } +#define NAND_BIG_DELAY_US 25 +#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ -#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ -#define SECTORSIZE 512 -#define NAND_NO_RB - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 #define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ #define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ #define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */ +#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ #define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */ #define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ -#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ -#define NAND_DISABLE_CE(nand) do \ +#define MACRO_NAND_DISABLE_CE(nandptr) do \ { \ - switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ + switch((unsigned long)nandptr) \ { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \ @@ -215,9 +248,9 @@ } \ } while(0) -#define NAND_ENABLE_CE(nand) do \ +#define MACRO_NAND_ENABLE_CE(nandptr) do \ { \ - switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ + switch((unsigned long)nandptr) \ { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \ @@ -228,7 +261,7 @@ } \ } while(0) -#define NAND_CTL_CLRALE(nandptr) do \ +#define MACRO_NAND_CTL_CLRALE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -241,7 +274,7 @@ } \ } while(0) -#define NAND_CTL_SETALE(nandptr) do \ +#define MACRO_NAND_CTL_SETALE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -254,7 +287,7 @@ } \ } while(0) -#define NAND_CTL_CLRCLE(nandptr) do \ +#define MACRO_NAND_CTL_CLRCLE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -267,7 +300,7 @@ } \ } while(0) -#define NAND_CTL_SETCLE(nandptr) do { \ +#define MACRO_NAND_CTL_SETCLE(nandptr) do { \ switch((unsigned long)nandptr) { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \ @@ -278,6 +311,17 @@ } \ } while(0) +#if 0 +#define SECTORSIZE 512 +#define NAND_NO_RB + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 + #ifdef NAND_NO_RB /* constant delay (see also tR in the datasheet) */ #define NAND_WAIT_READY(nand) do { \ @@ -292,7 +336,7 @@ #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - +#endif /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -325,9 +369,19 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 + +/* Reserve 256 kB for Monitor */ +/* #define CFG_FLASH_BASE 0xFFFC0000 #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_LEN (256 * 1024) +*/ + +/* Reserve 320 kB for Monitor */ +#define CFG_FLASH_BASE 0xFFFB0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (320 * 1024) + #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ /* @@ -358,11 +412,6 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#if 0 /* test-only */ -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - /*----------------------------------------------------------------------- * Environment Variable setup */ @@ -380,6 +429,8 @@ #define CFG_ENV_ADDR_REDUND 0xFFFFA000 #define CFG_ENV_SIZE_REDUND 0x2000 +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + #endif /* ENVIRONMENT_IN_EEPROM */ @@ -403,16 +454,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * @@ -455,7 +496,7 @@ #define CONFIG_VGA_AS_SINGLE_DEVICE /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ #define CFG_ISA_IO 0xE8000000 -/* see also drivers/videomodes.c */ +/* see also drivers/video/videomodes.c */ #define CFG_DEFAULT_VIDEO_MODE 0x303 #endif @@ -511,7 +552,6 @@ #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -532,7 +572,7 @@ #define CFG_GPIO0_OSRH 0x40000550 #define CFG_GPIO0_OSRL 0x00000110 #define CFG_GPIO0_ISR1H 0x00000000 -/*#define CFG_GPIO0_ISR1L 0x15555445*/ +/*#define CFG_GPIO0_ISR1L 0x15555445*/ #define CFG_GPIO0_ISR1L 0x15555444 #define CFG_GPIO0_TSRH 0x00000000 #define CFG_GPIO0_TSRL 0x00000000 @@ -548,8 +588,9 @@ #define CONFIG_NO_SERIAL_EEPROM -/*#undef CONFIG_NO_SERIAL_EEPROM*/ + /*--------------------------------------------------------------------*/ + #ifdef CONFIG_NO_SERIAL_EEPROM /* @@ -674,7 +715,6 @@ #define PLL_PCIDIV_3 0x00000002 #define PLL_PCIDIV_4 0x00000003 - #ifdef CONFIG_PPCHAMELEON_CLK_25 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */ #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ @@ -742,27 +782,54 @@ #if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) /* Model HI */ -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55 +#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55 +#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55 #define CFG_OPB_FREQ 55555555 /* Model ME */ #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33 +#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33 +#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33 #define CFG_OPB_FREQ 66666666 #else /* Model BA (default) */ -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33 +#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33 +#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33 #define CFG_OPB_FREQ 66666666 #endif -#endif +#endif /* CONFIG_NO_SERIAL_EEPROM */ -#define CONFIG_JFFS2_NAND 0 /* jffs2 on nand support */ -#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */ -#define CONFIG_JFFS2_NAND_OFF 0 /* start of jffs2 partition */ -#define CONFIG_JFFS2_NAND_SIZE 2*1024*1024 /* size of jffs2 partition */ +#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ #define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ +/* + * JFFS2 partitions + */ + +/* No command line, one static partition */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nand0" +#define CONFIG_JFFS2_PART_SIZE 0x00400000 +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=PPChameleon-0,nand0=ppchameleonevb-nand" +*/ + +/* 256 kB U-boot image */ +/* +#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \ + "1792k(user),256k(u-boot);" \ + "ppchameleonevb-nand:-(nand)" +*/ + +/* 320 kB U-boot image */ +/* +#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \ + "1728k(user),320k(u-boot);" \ + "ppchameleonevb-nand:-(nand)" +*/ + #endif /* __CONFIG_H */