X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FPPChameleonEVB.h;h=e4ad1fbd876b5aa0f37e7e673d0db2d6464cf6ca;hb=e6325153874b567eece9c4ac294c4b82ec7b4004;hp=c2c372a4497f2e38b81d592ca2513957d6f2724b;hpb=b79a11cc2bda7a4d5e00444427a0d06b4e86a990;p=u-boot diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index c2c372a449..e4ad1fbd87 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -38,6 +38,21 @@ #define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA #endif + +/* Only one of the following two symbols must be defined (default is 25 MHz) + * CONFIG_PPCHAMELEON_CLK_25 + * CONFIG_PPCHAMELEON_CLK_33 + */ +#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33)) +#define CONFIG_PPCHAMELEON_CLK_33 +#endif + +#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33)) +#error "* Two external frequencies (SysClk) are defined! *" +#endif + +#undef CONFIG_PPCHAMELEON_SMI712 + /* * Debug stuff */ @@ -60,7 +75,14 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +#ifdef CONFIG_PPCHAMELEON_CLK_25 +# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ +#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) +# define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ +#else +# error "* External frequency (SysClk) not defined! *" +#endif #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ @@ -70,17 +92,19 @@ /* Ethernet stuff */ #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ #define CONFIG_ETHADDR 00:50:c2:1e:af:fe +#define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - #undef CONFIG_EXT_PHY +#define CONFIG_NET_MULTI 1 #define CONFIG_MII 1 /* MII PHY management */ #ifndef CONFIG_EXT_PHY -#define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CONFIG_PHY_ADDR 0 /* EMAC0 PHY address */ +#define CONFIG_PHY1_ADDR 1 /* EMAC1 PHY address */ #else #define CONFIG_PHY_ADDR 2 /* PHY address */ #endif @@ -92,8 +116,10 @@ CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ + CFG_CMD_JFFS2 | \ CFG_CMD_MII | \ - CFG_CMD_NAND ) + CFG_CMD_NAND | \ + CFG_CMD_PCI ) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -103,8 +129,9 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ +#define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */ +#define CFG_I2C_RTC_ADDR 0x68 +#define CFG_M41T11_BASE_YEAR 1900 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -135,9 +162,9 @@ #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 +#define CFG_BASE_BAUD 691200 /* The following table includes the supported baudrates */ #define CFG_BAUDRATE_TABLE \ @@ -180,7 +207,6 @@ #define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ #define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ - #define NAND_DISABLE_CE(nand) do \ { \ switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ @@ -207,7 +233,6 @@ } \ } while(0) - #define NAND_CTL_CLRALE(nandptr) do \ { \ switch((unsigned long)nandptr) \ @@ -288,9 +313,10 @@ #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */ #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ + #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ #define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ @@ -338,17 +364,29 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #if 0 /* test-only */ -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ #endif /*----------------------------------------------------------------------- * Environment Variable setup */ +#ifdef ENVIRONMENT_IN_EEPROM + #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ +#define CFG_ENV_SIZE 0x700 /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/ + +#else /* DEFAULT: environment in flash, using redundand flash sectors */ + +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#define CFG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */ +#define CFG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/ +#define CFG_ENV_ADDR_REDUND 0xFFFFA000 +#define CFG_ENV_SIZE_REDUND 0x2000 + +#endif /* ENVIRONMENT_IN_EEPROM */ + #define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ #define CFG_NVRAM_SIZE 242 /* NVRAM size */ @@ -409,23 +447,21 @@ #define CFG_EBC_PB3AP 0x92015480 #define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */ - -#if 0 /* Roese */ -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR 0xFF858000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (CAN0, 1) initialization */ -#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (CompactFlash IDE) initialization */ -#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (NVRAM/RTC) initialization */ -#define CFG_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */ -#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ +#ifdef CONFIG_PPCHAMELEON_SMI712 +/* + * Video console (graphic: SMI LynxEM) + */ +#define CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SMI_LYNXEM +#define CONFIG_VIDEO_LOGO +/*#define CONFIG_VIDEO_BMP_LOGO*/ +#define CONFIG_CONSOLE_EXTRA_INFO +#define CONFIG_VGA_AS_SINGLE_DEVICE +/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ +#define CFG_ISA_IO 0xE8000000 +/* see also drivers/videomodes.c */ +#define CFG_DEFAULT_VIDEO_MODE 0x303 #endif /*----------------------------------------------------------------------- @@ -458,34 +494,27 @@ #define CFG_FPGA_STATUS_FLASH 0x0008 #define CFG_FPGA_STATUS_TS_IRQ 0x1000 -#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ +#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ +#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ /* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ +#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ +#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in data cache) */ -#if 0 /* test-only */ -#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */ - -#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#else /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 +#define CFG_TEMP_STACK_OCM 1 /* On Chip Memory location */ #define CFG_OCM_DATA_ADDR 0xF8000000 #define CFG_OCM_DATA_SIZE 0x1000 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#endif #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) @@ -507,7 +536,7 @@ #define CFG_GPIO0_OSRH 0x40000550 #define CFG_GPIO0_OSRL 0x00000110 #define CFG_GPIO0_ISR1H 0x00000000 -/*#define CFG_GPIO0_ISR1L 0x15555445*/ +/*#define CFG_GPIO0_ISR1L 0x15555445*/ #define CFG_GPIO0_ISR1L 0x15555444 #define CFG_GPIO0_TSRH 0x00000000 #define CFG_GPIO0_TSRL 0x00000000 @@ -523,10 +552,10 @@ #define CONFIG_NO_SERIAL_EEPROM -/*#undef CONFIG_NO_SERIAL_EEPROM*/ + /*--------------------------------------------------------------------*/ -#ifdef CONFIG_NO_SERIAL_EEPROM +#ifdef CONFIG_NO_SERIAL_EEPROM /* !----------------------------------------------------------------------- @@ -535,163 +564,209 @@ ! are plugged in the board will be utilized as non-ECC DIMMs. !----------------------------------------------------------------------- */ -#undef AUTO_MEMORY_CONFIG -#define DIMM_READ_ADDR 0xAB -#define DIMM_WRITE_ADDR 0xAA - - -#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ -#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ -#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ -#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ -#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ -#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ -#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ -#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ -#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ +#undef AUTO_MEMORY_CONFIG +#define DIMM_READ_ADDR 0xAB +#define DIMM_WRITE_ADDR 0xAA + +#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ +#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ +#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */ +#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ +#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ +#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ +#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ +#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ +#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ /* Defines for CPC0_PLLMR1 Register fields */ -#define PLL_ACTIVE 0x80000000 -#define CPC0_PLLMR1_SSCS 0x80000000 -#define PLL_RESET 0x40000000 -#define CPC0_PLLMR1_PLLR 0x40000000 +#define PLL_ACTIVE 0x80000000 +#define CPC0_PLLMR1_SSCS 0x80000000 +#define PLL_RESET 0x40000000 +#define CPC0_PLLMR1_PLLR 0x40000000 /* Feedback multiplier */ -#define PLL_FBKDIV 0x00F00000 -#define CPC0_PLLMR1_FBDV 0x00F00000 -#define PLL_FBKDIV_16 0x00000000 -#define PLL_FBKDIV_1 0x00100000 -#define PLL_FBKDIV_2 0x00200000 -#define PLL_FBKDIV_3 0x00300000 -#define PLL_FBKDIV_4 0x00400000 -#define PLL_FBKDIV_5 0x00500000 -#define PLL_FBKDIV_6 0x00600000 -#define PLL_FBKDIV_7 0x00700000 -#define PLL_FBKDIV_8 0x00800000 -#define PLL_FBKDIV_9 0x00900000 -#define PLL_FBKDIV_10 0x00A00000 -#define PLL_FBKDIV_11 0x00B00000 -#define PLL_FBKDIV_12 0x00C00000 -#define PLL_FBKDIV_13 0x00D00000 -#define PLL_FBKDIV_14 0x00E00000 -#define PLL_FBKDIV_15 0x00F00000 +#define PLL_FBKDIV 0x00F00000 +#define CPC0_PLLMR1_FBDV 0x00F00000 +#define PLL_FBKDIV_16 0x00000000 +#define PLL_FBKDIV_1 0x00100000 +#define PLL_FBKDIV_2 0x00200000 +#define PLL_FBKDIV_3 0x00300000 +#define PLL_FBKDIV_4 0x00400000 +#define PLL_FBKDIV_5 0x00500000 +#define PLL_FBKDIV_6 0x00600000 +#define PLL_FBKDIV_7 0x00700000 +#define PLL_FBKDIV_8 0x00800000 +#define PLL_FBKDIV_9 0x00900000 +#define PLL_FBKDIV_10 0x00A00000 +#define PLL_FBKDIV_11 0x00B00000 +#define PLL_FBKDIV_12 0x00C00000 +#define PLL_FBKDIV_13 0x00D00000 +#define PLL_FBKDIV_14 0x00E00000 +#define PLL_FBKDIV_15 0x00F00000 /* Forward A divisor */ -#define PLL_FWDDIVA 0x00070000 -#define CPC0_PLLMR1_FWDVA 0x00070000 -#define PLL_FWDDIVA_8 0x00000000 -#define PLL_FWDDIVA_7 0x00010000 -#define PLL_FWDDIVA_6 0x00020000 -#define PLL_FWDDIVA_5 0x00030000 -#define PLL_FWDDIVA_4 0x00040000 -#define PLL_FWDDIVA_3 0x00050000 -#define PLL_FWDDIVA_2 0x00060000 -#define PLL_FWDDIVA_1 0x00070000 +#define PLL_FWDDIVA 0x00070000 +#define CPC0_PLLMR1_FWDVA 0x00070000 +#define PLL_FWDDIVA_8 0x00000000 +#define PLL_FWDDIVA_7 0x00010000 +#define PLL_FWDDIVA_6 0x00020000 +#define PLL_FWDDIVA_5 0x00030000 +#define PLL_FWDDIVA_4 0x00040000 +#define PLL_FWDDIVA_3 0x00050000 +#define PLL_FWDDIVA_2 0x00060000 +#define PLL_FWDDIVA_1 0x00070000 /* Forward B divisor */ -#define PLL_FWDDIVB 0x00007000 -#define CPC0_PLLMR1_FWDVB 0x00007000 -#define PLL_FWDDIVB_8 0x00000000 -#define PLL_FWDDIVB_7 0x00001000 -#define PLL_FWDDIVB_6 0x00002000 -#define PLL_FWDDIVB_5 0x00003000 -#define PLL_FWDDIVB_4 0x00004000 -#define PLL_FWDDIVB_3 0x00005000 -#define PLL_FWDDIVB_2 0x00006000 -#define PLL_FWDDIVB_1 0x00007000 +#define PLL_FWDDIVB 0x00007000 +#define CPC0_PLLMR1_FWDVB 0x00007000 +#define PLL_FWDDIVB_8 0x00000000 +#define PLL_FWDDIVB_7 0x00001000 +#define PLL_FWDDIVB_6 0x00002000 +#define PLL_FWDDIVB_5 0x00003000 +#define PLL_FWDDIVB_4 0x00004000 +#define PLL_FWDDIVB_3 0x00005000 +#define PLL_FWDDIVB_2 0x00006000 +#define PLL_FWDDIVB_1 0x00007000 /* PLL tune bits */ -#define PLL_TUNE_MASK 0x000003FF -#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ -#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ -#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ -#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ -#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ -#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ -#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ +#define PLL_TUNE_MASK 0x000003FF +#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ +#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ +#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ +#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ +#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ +#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ +#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ /* Defines for CPC0_PLLMR0 Register fields */ /* CPU divisor */ -#define PLL_CPUDIV 0x00300000 -#define CPC0_PLLMR0_CCDV 0x00300000 -#define PLL_CPUDIV_1 0x00000000 -#define PLL_CPUDIV_2 0x00100000 -#define PLL_CPUDIV_3 0x00200000 -#define PLL_CPUDIV_4 0x00300000 +#define PLL_CPUDIV 0x00300000 +#define CPC0_PLLMR0_CCDV 0x00300000 +#define PLL_CPUDIV_1 0x00000000 +#define PLL_CPUDIV_2 0x00100000 +#define PLL_CPUDIV_3 0x00200000 +#define PLL_CPUDIV_4 0x00300000 /* PLB divisor */ -#define PLL_PLBDIV 0x00030000 -#define CPC0_PLLMR0_CBDV 0x00030000 -#define PLL_PLBDIV_1 0x00000000 -#define PLL_PLBDIV_2 0x00010000 -#define PLL_PLBDIV_3 0x00020000 -#define PLL_PLBDIV_4 0x00030000 +#define PLL_PLBDIV 0x00030000 +#define CPC0_PLLMR0_CBDV 0x00030000 +#define PLL_PLBDIV_1 0x00000000 +#define PLL_PLBDIV_2 0x00010000 +#define PLL_PLBDIV_3 0x00020000 +#define PLL_PLBDIV_4 0x00030000 /* OPB divisor */ -#define PLL_OPBDIV 0x00003000 -#define CPC0_PLLMR0_OPDV 0x00003000 -#define PLL_OPBDIV_1 0x00000000 -#define PLL_OPBDIV_2 0x00001000 -#define PLL_OPBDIV_3 0x00002000 -#define PLL_OPBDIV_4 0x00003000 +#define PLL_OPBDIV 0x00003000 +#define CPC0_PLLMR0_OPDV 0x00003000 +#define PLL_OPBDIV_1 0x00000000 +#define PLL_OPBDIV_2 0x00001000 +#define PLL_OPBDIV_3 0x00002000 +#define PLL_OPBDIV_4 0x00003000 /* EBC divisor */ -#define PLL_EXTBUSDIV 0x00000300 -#define CPC0_PLLMR0_EPDV 0x00000300 -#define PLL_EXTBUSDIV_2 0x00000000 -#define PLL_EXTBUSDIV_3 0x00000100 -#define PLL_EXTBUSDIV_4 0x00000200 -#define PLL_EXTBUSDIV_5 0x00000300 +#define PLL_EXTBUSDIV 0x00000300 +#define CPC0_PLLMR0_EPDV 0x00000300 +#define PLL_EXTBUSDIV_2 0x00000000 +#define PLL_EXTBUSDIV_3 0x00000100 +#define PLL_EXTBUSDIV_4 0x00000200 +#define PLL_EXTBUSDIV_5 0x00000300 /* MAL divisor */ -#define PLL_MALDIV 0x00000030 -#define CPC0_PLLMR0_MPDV 0x00000030 -#define PLL_MALDIV_1 0x00000000 -#define PLL_MALDIV_2 0x00000010 -#define PLL_MALDIV_3 0x00000020 -#define PLL_MALDIV_4 0x00000030 +#define PLL_MALDIV 0x00000030 +#define CPC0_PLLMR0_MPDV 0x00000030 +#define PLL_MALDIV_1 0x00000000 +#define PLL_MALDIV_2 0x00000010 +#define PLL_MALDIV_3 0x00000020 +#define PLL_MALDIV_4 0x00000030 /* PCI divisor */ -#define PLL_PCIDIV 0x00000003 -#define CPC0_PLLMR0_PPFD 0x00000003 -#define PLL_PCIDIV_1 0x00000000 -#define PLL_PCIDIV_2 0x00000001 -#define PLL_PCIDIV_3 0x00000002 -#define PLL_PCIDIV_4 0x00000003 - -/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */ -#define PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ +#define PLL_PCIDIV 0x00000003 +#define CPC0_PLLMR0_PPFD 0x00000003 +#define PLL_PCIDIV_1 0x00000000 +#define PLL_PCIDIV_2 0x00000001 +#define PLL_PCIDIV_3 0x00000002 +#define PLL_PCIDIV_4 0x00000003 + +#ifdef CONFIG_PPCHAMELEON_CLK_25 +/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */ +#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ +#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + +#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ +#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \ PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + +#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ +#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + +#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ +#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) +#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) + +/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */ +#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \ + PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ + PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_2) +#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) + +#else +#error "* External frequency (SysClk) not defined! *" +#endif + #if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) /* Model HI */ -#define PLLMR0_DEFAULT PLLMR0_333_111_37_55_55 -#define PLLMR1_DEFAULT PLLMR1_333_111_37_55_55 +#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55 +#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55 +#define CFG_OPB_FREQ 55555555 /* Model ME */ #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) -#define PLLMR0_DEFAULT PLLMR0_266_133_33_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_33_66_33 +#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33 +#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33 +#define CFG_OPB_FREQ 66666666 #else /* Model BA (default) */ -#define PLLMR0_DEFAULT PLLMR0_133_133_33_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_133_33_66_33 - +#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33 +#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33 +#define CFG_OPB_FREQ 66666666 #endif #endif /* CONFIG_NO_SERIAL_EEPROM */ +#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ +#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */ +#define CONFIG_JFFS2_NAND_OFF 0 /* start of jffs2 partition */ +#define CONFIG_JFFS2_NAND_SIZE 2*1024*1024 /* size of jffs2 partition */ +#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ + #endif /* __CONFIG_H */