X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FRBC823.h;h=e7e061cb3e3a1508dba088a2a15a1608f5e52897;hb=aafd2c5ddb9078c425c2edb8a6b5f5017895bea3;hp=3970dc36f12bdf116bb4b7c12c6289a2d868367b;hpb=aaf5e825606a70ddc8fca8e366d8c16a6fd3cc7c;p=u-boot

diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h
index 3970dc36f1..e7e061cb3e 100644
--- a/include/configs/RBC823.h
+++ b/include/configs/RBC823.h
@@ -119,7 +119,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -134,8 +133,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x0100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
@@ -262,8 +259,8 @@
  */
 #define SCCR_MASK	SCCR_EBDF11
 #define CONFIG_SYS_SCCR	(SCCR_RTDIV   | SCCR_RTSEL    | SCCR_CRQEN    | \
-		         SCCR_PRQEN   | SCCR_EBDF00   | \
-		         SCCR_COM01   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_PRQEN   | SCCR_EBDF00   | \
+			 SCCR_COM01   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD001 | \
 			 SCCR_DFALCD00)
 
@@ -344,7 +341,7 @@
 
 #define CONFIG_SYS_OR1_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_MSYS)
 #define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
-		          BR_PS_8 | BR_V)
+			  BR_PS_8 | BR_V)
 
 /*
  * BR4 and OR4 (SDRAM)