X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FSXNI855T.h;h=b7fbe5e153a011d6f7f0b7b75d71b6fcec1082e8;hb=e5f5c4a977c411c0cd3899a4f9487eea77a0e150;hp=cac04b4017a9beb6cc516e490d61424c29d23f93;hpb=68d7d65100e84df00bca971c114092731b441090;p=u-boot

diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h
index cac04b4017..b7fbe5e153 100644
--- a/include/configs/SXNI855T.h
+++ b/include/configs/SXNI855T.h
@@ -64,6 +64,8 @@
 #define CONFIG_MPC860T		1
 #define CONFIG_MPC855T		1
 
+#define	CONFIG_SYS_TEXT_BASE	0xF8000000
+
 #define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
 #undef	CONFIG_8xx_CONS_SMC2
 #undef	CONFIG_8xx_CONS_SCC1
@@ -163,75 +165,8 @@
 
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NAND
 #define CONFIG_CMD_DATE
 
-
-#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition */
-#undef CONFIG_CMD_MTDPARTS
-
-/*
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0x00780000
-#define CONFIG_JFFS2_PART_OFFSET	0x00080000
-*/
-
-#define CONFIG_JFFS2_DEV		"nand0"
-#define CONFIG_JFFS2_PART_SIZE		0x00200000
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		"nor0=sixnet-0,nand0=sixnet-nand"
-#define MTDPARTS_DEFAULT	"mtdparts=sixnet-0:7680k@512k();sixnet-nand:2m(jffs2-nand)"
-*/
-
-/* NAND flash support */
-#define CONFIG_NAND_LEGACY
-#define CONFIG_MTD_NAND_ECC_JFFS2
-#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices	*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-
-/* DFBUSY is available on Port C, bit 12; 0 if busy */
-#define NAND_WAIT_READY(nand)	\
-	while (!(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & 0x0008));
-#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND((d), (adr))
-#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND((d), (adr))
-#define WRITE_NAND(d, adr)	\
-	 do { (*(volatile uint8_t *)(adr) = (uint8_t)(d)); } while (0)
-#define READ_NAND(adr) (*(volatile uint8_t *)(adr))
-#define	CLE_LO	0x01	/* 0 selects CLE mode (CLE high) */
-#define	ALE_LO	0x02	/* 0 selects ALE mode (ALE high) */
-#define	CE_LO	0x04	/* 1 selects chip (CE low) */
-#define	nand_setcr(cr, val) do {*(volatile uint8_t*)(cr) = (val);} while (0)
-#define NAND_DISABLE_CE(nand) \
-	nand_setcr((nand)->IO_ADDR + 1, ALE_LO | CLE_LO)
-#define NAND_ENABLE_CE(nand) \
-	nand_setcr((nand)->IO_ADDR + 1, CE_LO | ALE_LO | CLE_LO)
-#define NAND_CTL_CLRALE(nandptr) \
-	nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
-#define NAND_CTL_SETALE(nandptr) \
-	nand_setcr((nandptr) + 1, CE_LO | CLE_LO)
-#define NAND_CTL_CLRCLE(nandptr) \
-	nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
-#define NAND_CTL_SETCLE(nandptr) \
-	nand_setcr((nandptr) + 1, CE_LO | ALE_LO)
-
 /*
  * Miscellaneous configurable options
  */
@@ -253,8 +188,6 @@
 
 #define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
@@ -270,9 +203,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -439,13 +371,6 @@
 #define DUART_BR5_VALUE ((CONFIG_SYS_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
 #define DUART_BR6_VALUE ((CONFIG_SYS_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
 
-/**********************************************************
- *
- * Boot Flags
- */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
 #define CONFIG_RESET_ON_PANIC		/* reset if system panic() */
 
 #define CONFIG_ENV_IS_IN_FLASH