X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FSandpoint8245.h;h=84e4891dc9ac19c226d5cf61138975c2a8f8c7e2;hb=0a7bec7f991950da90c6ee6bc59f322abebccbb7;hp=8cb920e0a101aaacad77036386552853ec81e76d;hpb=f82642e33899766892499b163e60560fbbf87773;p=u-boot

diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h
index 8cb920e0a1..84e4891dc9 100644
--- a/include/configs/Sandpoint8245.h
+++ b/include/configs/Sandpoint8245.h
@@ -39,6 +39,9 @@
 #define CONFIG_MPC8245		1
 #define CONFIG_SANDPOINT	1
 
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+#define CONFIG_SYS_LDSCRIPT	"board/sandpoint/u-boot.lds"
+
 #if 0
 #define USE_DINK32		1
 #else
@@ -94,7 +97,6 @@
 #define CONFIG_PCI				/* include pci support		*/
 #undef CONFIG_PCI_PNP
 
-#define CONFIG_NET_MULTI			/* Multi ethernet cards support */
 
 #define CONFIG_EEPRO100
 #define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
@@ -122,21 +124,18 @@
 #define CONFIG_SYS_MONITOR_BASE	0x00090000
 #define CONFIG_SYS_RAMBOOT		1
 #define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_INIT_RAM_END	0x10000
-#define CONFIG_SYS_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #else
 #undef	CONFIG_SYS_RAMBOOT
 #define CONFIG_SYS_MONITOR_LEN		0x00030000
-#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 
-/*#define CONFIG_SYS_GBL_DATA_SIZE    256*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_END      0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 #endif
 
@@ -195,7 +194,6 @@
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 #define CONFIG_SYS_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
 
 /*-----------------------------------------------------------------------
@@ -203,7 +201,7 @@
  */
 
 
-#define CONFIG_WINBOND_83C553	1	/*has a winbond bridge			*/
+/* #define CONFIG_WINBOND_83C553	1	/ *has a winbond bridge			*/
 #define CONFIG_SYS_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
 #define CONFIG_SYS_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
 #define CONFIG_SYS_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/
@@ -378,16 +376,6 @@
 #  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
-
-
 /* values according to the manual */
 
 #define CONFIG_DRAM_50MHZ	1