X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FT4240QDS.h;h=9d4baaa79fc1a0990a82db4ab0af76e59b92d475;hb=ee422142f454d54f0ed39a2cbf083ff12e98a3e1;hp=1d18316a4129dc51387c10cf925dbd9aa2f62ab6;hpb=4d6647ab17ab9d33c60f7a9f07576c5fbdf6336f;p=u-boot diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 1d18316a41..9d4baaa79f 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -12,7 +12,6 @@ #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE4 -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ @@ -24,7 +23,6 @@ #else #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x00201000 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 #define CONFIG_SPL_PAD_TO 0x40000 @@ -61,7 +59,6 @@ #define CONFIG_SPL_SKIP_RELOCATE #define CONFIG_SPL_COMMON_INIT_DDR #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#define CONFIG_SYS_NO_FLASH #endif #endif @@ -73,7 +70,6 @@ #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_NO_FLASH #endif #define CONFIG_SRIO_PCIE_BOOT_MASTER @@ -81,7 +77,7 @@ #include "t4qds.h" -#ifdef CONFIG_SYS_NO_FLASH +#ifndef CONFIG_MTD_NOR_FLASH #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) #define CONFIG_ENV_IS_NOWHERE #endif @@ -494,7 +490,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_LBA48 #define CONFIG_CMD_SATA -#define CONFIG_DOS_PARTITION #endif #ifdef CONFIG_FMAN_ENET @@ -517,14 +512,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_HAS_FSL_DR_USB -#define CONFIG_MMC - #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#define CONFIG_GENERIC_MMC -#define CONFIG_DOS_PARTITION #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 #define CONFIG_ESDHC_DETECT_QUIRK \ (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \