X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FTASREG.h;h=c93b12ebf1c46f2191a72891f4f31b29700e265e;hb=2f83cd57b67504f0c254f31862dfcc9baf791a3a;hp=18ffbfd72f09477c22a1a3d290bb712afd375ca2;hpb=f61f1e150c84f5b9347fca79a4bc5f2286c545d2;p=u-boot

diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h
index 18ffbfd72f..c93b12ebf1 100644
--- a/include/configs/TASREG.h
+++ b/include/configs/TASREG.h
@@ -189,9 +189,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_ENV_IS_IN_FLASH	1
@@ -206,7 +205,7 @@
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE		0xffc00000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
 
 #if 0 /* test-only */
 #define CONFIG_PRAM             512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
@@ -252,20 +251,31 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
 
 /* CS0 - AMD Flash, address 0xffc00000 */
-#define	CONFIG_SYS_CSAR0               0xffc0
-#define	CONFIG_SYS_CSCR0               0x1980          /* WS=0110, AA=1, PS=10         */
+#define	CONFIG_SYS_CS0_BASE		0xffc00000
+#define	CONFIG_SYS_CS0_CTRL		0x00001980	/* WS=0110, AA=1, PS=10         */
 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
-#define	CONFIG_SYS_CSMR0               0x003f0021      /* 4MB, AA=0, WP=0, C/I=1, V=1  */
+#define	CONFIG_SYS_CS0_MASK		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
 
 /* CS1 - FPGA, address 0xe0000000 */
-#define	CONFIG_SYS_CSAR1               0xe000
-#define	CONFIG_SYS_CSCR1               0x0d80          /* WS=0011, AA=1, PS=10         */
-#define	CONFIG_SYS_CSMR1               0x00010001      /* 128kB, AA=0, WP=0, C/I=0, V=1*/
+#define	CONFIG_SYS_CS1_BASE		0xe0000000
+#define	CONFIG_SYS_CS1_CTRL		0x00000d80	/* WS=0011, AA=1, PS=10         */
+#define	CONFIG_SYS_CS1_MASK		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
 
 /*-----------------------------------------------------------------------
  * Port configuration