X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FTQM85xx.h;h=79a958dc2aee4be940886be049afb29054a6b770;hb=95e39793312ab1ce01615f2b5330382e99ed6e81;hp=72db26c7b13c3dce27901bc99f6c206869af2412;hpb=8206bfae3ab7f99965136384360ba2de0c6f4c3b;p=u-boot diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 72db26c7b1..79a958dc2a 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -41,6 +41,12 @@ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ +#if defined(CONFIG_TQM8548_BE) +#define CONFIG_SYS_TEXT_BASE 0xfff80000 +#else +#define CONFIG_SYS_TEXT_BASE 0xfffc0000 +#endif + #if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE) #define CONFIG_TQM8548 #endif @@ -75,7 +81,7 @@ * NAND flash support (disabled by default) * * Warning: NAND support will likely increase the U-Boot image size - * to more than 256 KB. Please adjust TEXT_BASE if necessary. + * to more than 256 KB. Please adjust CONFIG_SYS_TEXT_BASE if necessary. */ #ifdef CONFIG_TQM8548_BE #define CONFIG_NAND @@ -137,14 +143,14 @@ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) - /* * DDR Setup */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#if defined(CONFIG_TQM_BIGFLASH) || \ + (!defined(CONFIG_TQM8548_AG) && !defined(CONFIG_TQM8548_BE)) +#define CONFIG_SYS_PPC_DDR_WIMGE (MAS2_I | MAS2_G) +#endif #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #ifdef CONFIG_TQM8548_AG #define CONFIG_VERY_BIG_RAM @@ -156,7 +162,7 @@ #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) /* TQM8540 & 8560 need DLL-override */ -#define CONFIG_DDR_DLL /* DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */ #endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */ @@ -165,15 +171,6 @@ #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ #endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */ -/* - * Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM - * series while new boards have 'N' type Flashes from the S29GLxxxN - * series, which have bigger sectors: 2 x 128 instead of 2 x 64 KB. - */ -#ifdef CONFIG_TQM8548 -#define CONFIG_TQM_FLASH_N_TYPE -#endif /* CONFIG_TQM8548 */ - /* * Flash on the Local Bus */ @@ -232,7 +229,7 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ /* * Note: when changing the Local Bus clock divider you have to @@ -250,13 +247,12 @@ #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_CCSRBAR \ + 0x04010000) /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End used area in RAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (~TEXT_BASE + 1)/* Reserved for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)/* Reserved for Monitor */ #define CONFIG_SYS_MALLOC_LEN (384 * 1024) /* Reserved for malloc */ /* Serial Port */ @@ -269,7 +265,6 @@ #else /* !CONFIG_TQM8560 */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -293,6 +288,7 @@ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " @@ -360,8 +356,6 @@ /* NAND FLASH */ #ifdef CONFIG_NAND -#undef CONFIG_NAND_LEGACY - #define CONFIG_NAND_FSL_UPM 1 #define CONFIG_MTD_NAND_ECC_JFFS2 1 /* use JFFS2 ECC */ @@ -371,35 +365,17 @@ #define CONFIG_SYS_NAND_CS_DIST 0x200 #define CONFIG_SYS_NAND_SIZE 0x8000 -#define CONFIG_SYS_NAND0_BASE (CONFIG_SYS_CCSRBAR + 0x03010000) -#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST) -#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST) -#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST) - -#define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ - -#if (CONFIG_SYS_MAX_NAND_DEVICE == 1) -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE } -#elif (CONFIG_SYS_MAX_NAND_DEVICE == 2) -#define CONFIG_SYS_NAND_QUIET_TEST 1 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \ - CONFIG_SYS_NAND1_BASE, \ -} -#elif (CONFIG_SYS_MAX_NAND_DEVICE == 4) -#define CONFIG_SYS_NAND_QUIET_TEST 1 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \ - CONFIG_SYS_NAND1_BASE, \ - CONFIG_SYS_NAND2_BASE, \ - CONFIG_SYS_NAND3_BASE, \ -} -#endif +#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_CCSRBAR + 0x03010000) + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define CONFIG_SYS_NAND_MAX_CHIPS 2 /* Number of chips per device */ /* CS3 for NAND Flash */ -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_NAND0_BASE & BR_BA) | BR_PS_8 | \ - BR_MS_UPMB | BR_V) +#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_NAND_BASE & BR_BA) | \ + BR_PS_8 | BR_MS_UPMB | BR_V) #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI) -#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */ +#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */ #endif /* CONFIG_NAND */ @@ -407,11 +383,11 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE (CONFIG_SYS_CCSRBAR + 0x02000000) -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE +#define CONFIG_SYS_PCI1_IO_BUS (CONFIG_SYS_CCSRBAR + 0x02000000) +#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ #ifdef CONFIG_PCIE1 @@ -420,16 +396,16 @@ * Addresses are mapped 1-1. */ #ifdef CONFIG_TQM_BIGFLASH -#define CONFIG_SYS_PCIE1_MEM_BASE 0xb0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xb0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0xaf000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0xaf000000 #else /* !CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_PCIE1_MEM_BASE 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0xef000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0xef000000 #endif /* CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE -#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BASE +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ #endif /* CONFIG_PCIE1 */ @@ -565,11 +541,7 @@ */ #define CONFIG_ENV_IS_IN_FLASH 1 -#ifdef CONFIG_TQM_FLASH_N_TYPE #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K (one sector) for env */ -#else /* !CONFIG_TQM_FLASH_N_TYPE */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ -#endif /* CONFIG_TQM_FLASH_N_TYPE */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) @@ -598,6 +570,8 @@ #define CONFIG_JFFS2_NAND 1 #ifdef CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nand0=TQM85xx-nand" #define MTDPARTS_DEFAULT "mtdparts=TQM85xx-nand:-" #else @@ -624,6 +598,7 @@ #define CONFIG_CMD_EEPROM #define CONFIG_CMD_DTT #define CONFIG_CMD_MII +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI @@ -657,14 +632,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ @@ -693,12 +660,12 @@ MK_STR(CONFIG_HOSTNAME)".dtb\0" #define CONFIG_ENV_BOOTFILE "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0" #define CONFIG_ENV_UBOOT "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \ - "uboot_addr="MK_STR(TEXT_BASE)"\0" + "uboot_addr="MK_STR(CONFIG_SYS_TEXT_BASE)"\0" #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_ENV_BOOTFILE \ CONFIG_ENV_FDT_FILE \ - CONFIG_ENV_CONSDEV \ + CONFIG_ENV_CONSDEV \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath\0" \ @@ -722,12 +689,11 @@ "fdt_addr=ffec0000\0" \ "kernel_addr=ffd00000\0" \ "ramdisk_addr=ff800000\0" \ - CONFIG_ENV_UBOOT \ + CONFIG_ENV_UBOOT \ "load=tftp 100000 $uboot\0" \ "update=protect off $uboot_addr +$filesize;" \ "erase $uboot_addr +$filesize;" \ - "cp.b 100000 $uboot_addr $filesize;" \ - "setenv filesize;saveenv\0" \ + "cp.b 100000 $uboot_addr $filesize" \ "upd=run load update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self"