X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FTQM862L.h;h=f03690a7b21b92041bcee7178db21adffd843bb0;hb=2f5df47351910a2936c7741cf111855829200943;hp=653d0c79aebab4ca8d8c90e9bb13e9bf1f76120d;hpb=3b57fe0a70b903f4db66c558bb9828bc58acf06b;p=u-boot

diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index 653d0c79ae..f03690a7b2 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000, 2001, 2002
+ * (C) Copyright 2000-2005
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -45,9 +45,9 @@
 
 #define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#define	CONFIG_BOOTCOUNT_LIMIT
 
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
@@ -58,19 +58,20 @@
 #undef	CONFIG_BOOTARGS
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=$(serverip):$(rootpath)\0"			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs $(bootargs) "				\
-		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
-		":$(hostname):$(netdev):off panic=1\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
 	"flash_nfs=run nfsargs addip;"					\
-		"bootm $(kernel_addr)\0"				\
+		"bootm ${kernel_addr}\0"				\
 	"flash_self=run ramargs addip;"					\
-		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
-	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
 	"rootpath=/opt/eldk/ppc_8xx\0"					\
-	"bootfile=/tftpboot/TQM860L/uImage\0"				\
+	"bootfile=/tftpboot/TQM862L/uImage\0"				\
 	"kernel_addr=40040000\0"					\
 	"ramdisk_addr=40100000\0"					\
 	""
@@ -94,9 +95,11 @@
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_IDE	| \
-				CFG_CMD_DATE	)
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -107,9 +110,8 @@
 #define	CFG_LONGHELP			/* undef to save memory		*/
 #define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
-#if 0
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #ifdef	CFG_HUSH_PARSER
 #define	CFG_PROMPT_HUSH_PS2	"> "
 #endif
@@ -179,6 +181,7 @@
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CFG_ENV_IS_IN_FLASH	1
+
 #define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
 #define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
@@ -250,15 +253,8 @@
  *-----------------------------------------------------------------------
  * Reset PLL lock status sticky bit, timer expired status bit and timer
  * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  */
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_PLPRCR							\
-		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 50 MHz we use a 1:1 clock */
 #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif	/* CONFIG_80MHz */
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -267,17 +263,9 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CFG_SCCR	(/* SCCR_TBS  | */ \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
-#else			/* up to 50 MHz we use a 1:1 clock */
-#define CFG_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif	/* CONFIG_80MHz */
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
@@ -334,7 +322,7 @@
  */
 
 #define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #1	*/
 
 /* used to re-map FLASH both when starting from SRAM or FLASH:
  * restrict access enough to keep SRAM working (if any)
@@ -346,19 +334,8 @@
 /*
  * FLASH timing:
  */
-#if   defined(CONFIG_80MHz)
-/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
-				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#elif defined(CONFIG_66MHz)
-/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
 #define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#else		/*   50 MHz */
-/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
-#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
-#endif	/*CONFIG_??MHz */
 
 #define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
@@ -415,17 +392,14 @@
  * --------------------------------------------
  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
  *
- * 50 MHz => 50.000.000 / Divider =  98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
+ *  50 MHz =>  50.000.000 / Divider =  98
+ *  66 Mhz =>  66.000.000 / Divider = 129
+ *  80 Mhz =>  80.000.000 / Divider = 156
+ * 100 Mhz => 100.000.000 / Divider = 195
  */
-#if   defined(CONFIG_80MHz)
-#define CFG_MAMR_PTA		156
-#elif defined(CONFIG_66MHz)
-#define CFG_MAMR_PTA		129
-#else		/*   50 MHz */
-#define CFG_MAMR_PTA		 98
-#endif	/*CONFIG_??MHz */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98
 
 /*
  * For 16 MBit, refresh rates could be 31.3 us