X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FVCMA9.h;h=ebe9e424c329ff25419dc6fd21f899e7b50d3019;hb=2a9a2339a4ea04636ed0968e76eeaf784e987f52;hp=7edea6a0478bbf6547e6ae2b72ae0e6c50337b9b;hpb=462b1038738dd86f8dd70595f250ce792e90d244;p=u-boot

diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 7edea6a047..ebe9e424c3 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -33,9 +33,10 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
-#define	CONFIG_S3C2410		1	/* in a SAMSUNG S3C2410 SoC     */
-#define CONFIG_VCMA9		1	/* on a MPL VCMA9 Board  */
+#define CONFIG_ARM920T	1	/* This is an ARM920T Core	*/
+#define CONFIG_S3C24X0	1	/* in a SAMSUNG S3C24x0-type SoC	*/
+#define CONFIG_S3C2410	1	/* specifically a SAMSUNG S3C2410 SoC	*/
+#define CONFIG_VCMA9	1	/* on a MPL VCMA9 Board  */
 
 /* input clock of PLL */
 #define CONFIG_SYS_CLK_FREQ	12000000/* VCMA9 has 12MHz input clock	*/
@@ -100,7 +101,6 @@
  * Size of malloc() pool
  */
 /*#define CONFIG_MALLOC_SIZE	(CONFIG_ENV_SIZE + 128*1024)*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* BUNZIP2 needs a lot of RAM */
@@ -108,9 +108,10 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_DRIVER_CS8900	1		/* we have a CS8900 on-board */
-#define CS8900_BASE		0x20000300
-#define CS8900_BUS16		1		/* the Linux driver does accesses as shorts */
+#define CONFIG_NET_MULTI
+#define CONFIG_CS8900		/* we have a CS8900 on-board */
+#define CONFIG_CS8900_BASE	0x20000300
+#define CONFIG_CS8900_BUS16	/* the Linux driver does accesses as shorts */
 
 #define CONFIG_DRIVER_S3C24X0_I2C	1	/* we use the buildin I2C controller */
 
@@ -246,42 +247,4 @@
 
 #define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
 
-/*-----------------------------------------------------------------------
- * NAND flash settings
- */
-#if defined(CONFIG_CMD_NAND)
-
-#define CONFIG_NAND_LEGACY
-#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-
-#define NAND_WAIT_READY(nand)	NF_WaitRB()
-
-#define NAND_DISABLE_CE(nand)	NF_SetCE(NFCE_HIGH)
-#define NAND_ENABLE_CE(nand)	NF_SetCE(NFCE_LOW)
-
-
-#define WRITE_NAND_COMMAND(d, adr)	NF_Cmd(d)
-#define WRITE_NAND_COMMANDW(d, adr)	NF_CmdW(d)
-#define WRITE_NAND_ADDRESS(d, adr)	NF_Addr(d)
-#define WRITE_NAND(d, adr)		NF_Write(d)
-#define READ_NAND(adr)			NF_Read()
-/* the following functions are NOP's because S3C24X0 handles this in hardware */
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
-
-#define CONFIG_MTD_NAND_VERIFY_WRITE	1
-#define CONFIG_MTD_NAND_ECC_JFFS2	1
-
-#endif
-
 #endif	/* __CONFIG_H */