X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FW7OLMC.h;h=bb6b6b9d26c1bce7bbe9bc4ec981f08cbefb729c;hb=3070a9a3cb41ed6b19f79590f7713d5685ab1066;hp=fd810961d0ecedaf2ab23d26c8ff0f579787ee72;hpb=a5562901661bd428f7e5feb333f796372cb81019;p=u-boot

diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h
index fd810961d0..bb6b6b9d26 100644
--- a/include/configs/W7OLMC.h
+++ b/include/configs/W7OLMC.h
@@ -70,6 +70,15 @@
 
 #define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
 
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
 /*
  * Command line configuration.
  */
@@ -145,10 +154,10 @@
 #define CFG_PCI_SUBSYS_DEVICEID 0x0156		/* PCI Device ID: 405GP		*/
 #define CFG_PCI_PTM1LA		0x00000000	/* point to sdram		*/
 #define CFG_PCI_PTM1MS		0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI 	0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA		0x00000000	/* disabled		*/
-#define CFG_PCI_PTM2MS		0x00000000	/* disabled		*/
-#define CFG_PCI_PTM2PCI 	0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM1PCI		0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA		0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2MS		0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2PCI		0x00000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * Set up values for external bus controller
@@ -281,15 +290,6 @@
  */
 #define SPD_EEPROM_ADDRESS      0x50	/* XXX conflicting address!!! XXX */
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		8192		/* For AMCC 405 CPUs			*/
-#define CFG_CACHELINE_SIZE	32		/* ...		*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5		/* log base 2 of the above val. */
-#endif
-
 /*
  * Init Memory Controller:
  */