X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fadp-ag101p.h;h=2499b39c16da9a1364af9b94c14e957921b68e16;hb=44da3a176c5bd48b7ed257454e3e551c956adb30;hp=48afbf4467d07ad438054b7dac93c897f5c0036c;hpb=326ea986ac150acdc7656d57fca647db80b50158;p=u-boot

diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h
index 48afbf4467..2499b39c16 100644
--- a/include/configs/adp-ag101p.h
+++ b/include/configs/adp-ag101p.h
@@ -9,7 +9,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/arch/ag101.h>
+#include <asm/arch-ag101/ag101.h>
 
 /*
  * CPU and Board Configuration Options
@@ -20,32 +20,33 @@
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
+#define CONFIG_SYS_GENERIC_GLOBAL_DATA
+
 /*
  * Definitions related to passing arguments to kernel.
  */
 #define CONFIG_CMDLINE_TAG			/* send commandline to Kernel */
 #define CONFIG_SETUP_MEMORY_TAGS	/* send memory definition to kernel */
 #define CONFIG_INITRD_TAG			/* send initrd params */
+#define CONFIG_NEEDS_MANUAL_RELOC
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_MEM_REMAP
 #endif
 
 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_TEXT_BASE	0x03200000
+#define CONFIG_SYS_TEXT_BASE	0x00500000
+#else
+#ifdef CONFIG_MEM_REMAP
+#define CONFIG_SYS_TEXT_BASE	0x80000000
 #else
 #define CONFIG_SYS_TEXT_BASE	0x00000000
 #endif
+#endif
 
 /*
  * Timer
  */
-
-/*
- * According to the discussion in u-boot mailing list before,
- * CONFIG_SYS_HZ at 1000 is mandatory.
- */
-#define CONFIG_SYS_HZ		1000
 #define CONFIG_SYS_CLK_FREQ	39062500
 #define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
 
@@ -86,7 +87,6 @@
 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
 #define CONFIG_BAUDRATE			38400
 #define CONFIG_CONS_INDEX		1
-#define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
 #define CONFIG_SYS_NS16550_REG_SIZE	-4
@@ -115,8 +115,6 @@
 /*
  * Command line configuration.
  */
-#include <config_cmd_default.h>
-
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_PING
@@ -125,7 +123,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_PROMPT	"NDS32 # "	/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 
 /* Print Buffer Size */
@@ -144,11 +141,6 @@
 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
 #define CONFIG_SYS_MALLOC_LEN		(512 << 10)
 
-/*
- * size in bytes reserved for initial data
- */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
-
 /*
  * AHB Controller configuration
  */
@@ -239,20 +231,33 @@
 /*
  * Physical Memory Map
  */
-#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
-#define PHYS_SDRAM_0		0x00000000	/* SDRAM Bank #1 */
-#if defined(CONFIG_MEM_REMAP)
-#define PHYS_SDRAM_0_AT_INIT	0x10000000	/* SDRAM Bank #1 before remap*/
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define PHYS_SDRAM_0	0x00000000  /* SDRAM Bank #1 */
+#else
+#ifdef CONFIG_MEM_REMAP
+#define PHYS_SDRAM_0	0x00000000	/* SDRAM Bank #1 */
+#else
+#define PHYS_SDRAM_0	0x80000000	/* SDRAM Bank #1 */
 #endif
-#else	/* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
-#define PHYS_SDRAM_0		0x10000000	/* SDRAM Bank #1 */
 #endif
+
 #define PHYS_SDRAM_1 \
 	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)	/* SDRAM Bank #2 */
 
 #define CONFIG_NR_DRAM_BANKS	2		/* we have 2 bank of DRAM */
-#define PHYS_SDRAM_0_SIZE	0x04000000	/* 64 MB */
-#define PHYS_SDRAM_1_SIZE	0x04000000	/* 64 MB */
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define PHYS_SDRAM_0_SIZE	0x20000000	/* 512 MB */
+#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512 MB */
+#else
+#ifdef CONFIG_MEM_REMAP
+#define PHYS_SDRAM_0_SIZE	0x20000000	/* 512 MB */
+#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512 MB */
+#else
+#define PHYS_SDRAM_0_SIZE	0x08000000	/* 128 MB */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
+#endif
+#endif
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0
 
@@ -332,19 +337,20 @@
 
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 
 /* support JEDEC */
 
 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
-#define PHYS_FLASH_1			0x80400000	/* BANK 1 */
-#else	/* !CONFIG_SKIP_LOWLEVEL_INIT */
+#define PHYS_FLASH_1			0x80000000	/* BANK 0 */
+#else
 #ifdef CONFIG_MEM_REMAP
 #define PHYS_FLASH_1			0x80000000	/* BANK 0 */
 #else
 #define PHYS_FLASH_1			0x00000000	/* BANK 0 */
+#endif
 #endif	/* CONFIG_MEM_REMAP */
-#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
 
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
@@ -359,11 +365,12 @@
  * but we have only 1 bank connected to flash on board
  */
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 
 /* max number of sectors on one chip */
-#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2*2)
+#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2)
 #define CONFIG_ENV_SECT_SIZE		CONFIG_FLASH_SECTOR_SIZE
-#define CONFIG_SYS_MAX_FLASH_SECT	128
+#define CONFIG_SYS_MAX_FLASH_SECT	512
 
 /* environments */
 #define CONFIG_ENV_IS_IN_FLASH