X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fads5121.h;h=4226529eb7ddee16bd78ce66f9919da72c0b1a6f;hb=3070a9a3cb41ed6b19f79590f7713d5685ab1066;hp=65dc97ebddf5211eddde80c1992472d128afca45;hpb=093e14c52280b4bcc84948bac605ee4d6e87b6e9;p=u-boot

diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index 65dc97ebdd..4226529eb7 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007 DENX Software Engineering
+ * (C) Copyright 2007, 2008 DENX Software Engineering
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -45,14 +45,25 @@
  */
 #define CONFIG_E300		1	/* E300 Family */
 #define CONFIG_MPC512X		1	/* MPC512X family */
+#define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
+
+/* video */
+#undef CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#endif
 
 /* CONFIG_PCI is defined at config time */
 
 #define CFG_MPC512X_CLKIN	66000000	/* in Hz */
 
 #define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R
 
 #define CFG_IMMR		0x80000000
+#define CFG_DIU_ADDR		(CFG_IMMR+0x2100)
 
 #define CFG_MEMTEST_START	0x00200000      /* memtest region */
 #define CFG_MEMTEST_END		0x00400000
@@ -127,28 +138,28 @@
 #define CFG_MICRON_OCD_DEFAULT	0x01010780
 
 /* DDR Priority Manager Configuration */
-#define CFG_MDDRCGRP_PM_CFG1	0x000777AA
-#define CFG_MDDRCGRP_PM_CFG2	0x00000055
-#define CFG_MDDRCGRP_HIPRIO_CFG	0x00000000
-#define CFG_MDDRCGRP_LUT0_MU    0x11111117
-#define CFG_MDDRCGRP_LUT0_ML	0x7777777A
-#define CFG_MDDRCGRP_LUT1_MU    0x4444EEEE
-#define CFG_MDDRCGRP_LUT1_ML	0xEEEEEEEE
-#define CFG_MDDRCGRP_LUT2_MU    0x44444444
+#define CFG_MDDRCGRP_PM_CFG1	0x00077777
+#define CFG_MDDRCGRP_PM_CFG2	0x00000000
+#define CFG_MDDRCGRP_HIPRIO_CFG	0x00000001
+#define CFG_MDDRCGRP_LUT0_MU	0xFFEEDDCC
+#define CFG_MDDRCGRP_LUT0_ML	0xBBAAAAAA
+#define CFG_MDDRCGRP_LUT1_MU	0x66666666
+#define CFG_MDDRCGRP_LUT1_ML	0x55555555
+#define CFG_MDDRCGRP_LUT2_MU	0x44444444
 #define CFG_MDDRCGRP_LUT2_ML	0x44444444
-#define CFG_MDDRCGRP_LUT3_MU    0x55555555
+#define CFG_MDDRCGRP_LUT3_MU	0x55555555
 #define CFG_MDDRCGRP_LUT3_ML	0x55555558
-#define CFG_MDDRCGRP_LUT4_MU    0x11111111
-#define CFG_MDDRCGRP_LUT4_ML	0x1111117C
-#define CFG_MDDRCGRP_LUT0_AU    0x33333377
-#define CFG_MDDRCGRP_LUT0_AL	0x7777EEEE
-#define CFG_MDDRCGRP_LUT1_AU    0x11111111
-#define CFG_MDDRCGRP_LUT1_AL	0x11111111
-#define CFG_MDDRCGRP_LUT2_AU    0x11111111
+#define CFG_MDDRCGRP_LUT4_MU	0x11111111
+#define CFG_MDDRCGRP_LUT4_ML	0x11111122
+#define CFG_MDDRCGRP_LUT0_AU	0xaaaaaaaa
+#define CFG_MDDRCGRP_LUT0_AL	0xaaaaaaaa
+#define CFG_MDDRCGRP_LUT1_AU	0x66666666
+#define CFG_MDDRCGRP_LUT1_AL	0x66666666
+#define CFG_MDDRCGRP_LUT2_AU	0x11111111
 #define CFG_MDDRCGRP_LUT2_AL	0x11111111
-#define CFG_MDDRCGRP_LUT3_AU    0x11111111
+#define CFG_MDDRCGRP_LUT3_AU	0x11111111
 #define CFG_MDDRCGRP_LUT3_AL	0x11111111
-#define CFG_MDDRCGRP_LUT4_AU    0x11111111
+#define CFG_MDDRCGRP_LUT4_AU	0x11111111
 #define CFG_MDDRCGRP_LUT4_AL	0x11111111
 
 /*
@@ -161,7 +172,7 @@
 #define CFG_FLASH_USE_BUFFER_WRITE
 
 #define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_FLASH_BANKS_LIST 	{CFG_FLASH_BASE}
+#define CFG_FLASH_BANKS_LIST	{CFG_FLASH_BASE}
 #define CFG_MAX_FLASH_SECT	256		/* max sectors per device */
 
 #undef CFG_FLASH_CHECKSUM
@@ -189,7 +200,11 @@
 
 #define CFG_MONITOR_BASE	TEXT_BASE		/* Start of monitor */
 #define CFG_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(512 * 1024)		/* Reserved for malloc */
+#ifdef	CONFIG_FSL_DIU_FB
+#define CFG_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
+#else
+#define CFG_MALLOC_LEN		(512 * 1024)
+#endif
 
 /*
  * Serial Port
@@ -357,6 +372,8 @@
 #define CFG_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
 #define CFG_HID2	HID2_HBE
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /*
  * Internal Definitions
  *
@@ -377,6 +394,7 @@
 
 #define CONFIG_HOSTNAME		ads5121
 #define CONFIG_BOOTFILE		ads5121/uImage
+#define CONFIG_ROOTPATH		/opt/eldk/pcc_6xx
 
 #define CONFIG_LOADADDR		400000	/* default location for tftp and bootm */
 
@@ -386,16 +404,16 @@
 #define CONFIG_BAUDRATE		115200
 
 #define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 	"echo"
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"u-boot_addr_r=200000\0"					\
-	"kernel_addr_r=200000\0"					\
+	"kernel_addr_r=300000\0"					\
 	"fdt_addr_r=400000\0"						\
 	"ramdisk_addr_r=500000\0"					\
 	"u-boot_addr=FFF00000\0"					\
-	"kernel_addr=FC000000\0"					\
+	"kernel_addr=FC040000\0"					\
 	"fdt_addr=FC2C0000\0"						\
 	"ramdisk_addr=FC300000\0"					\
 	"ramdiskfile=ads5121/uRamdisk\0"				\
@@ -412,7 +430,7 @@
 	"addtty=setenv bootargs ${bootargs} "				\
 		"console=${consdev},${baudrate}\0"			\
 	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr_r} - ${fdt_addr}\0"		\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
 	"flash_self=run ramargs addip addtty;"				\
 		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
 	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
@@ -421,10 +439,10 @@
 		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
 	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
 		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
-		"tftp ${fdt_addr} ${fdtfile};"				\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
 		"run ramargs addip addtty;"				\
-		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr}\0"\
-	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
+	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
 	"update=protect off ${u-boot_addr} +${filesize};"		\
 		"era ${u-boot_addr} +${filesize};"			\
 		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\