X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Faria.h;h=c5f9cc1046f747452bc03c1a61c777076b6c329e;hb=d03f4230a6cc08ac718c876309e4dc425e1a9854;hp=fb374722e5135e59bda118dfe554cd1108ead74e;hpb=a6d6d46a4fef876455e11b45ed699c0fb3bd1ca1;p=u-boot

diff --git a/include/configs/aria.h b/include/configs/aria.h
index fb374722e5..c5f9cc1046 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -78,6 +78,9 @@
 #define CONFIG_SYS_DDR_SIZE		256		/* MB */
 #define CONFIG_SYS_DDR_BASE		0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_MAX_RAM_SIZE		0x20000000
+
+#define CONFIG_SYS_IOCTRL_MUX_DDR	0x00000036
 
 /* DDR Controller Configuration
  *
@@ -126,7 +129,7 @@
 #define CONFIG_SYS_MDDRC_SYS_CFG     (	(1 << 31) |	/* RST_B */ \
 					(1 << 30) |	/* CKE */ \
 					(1 << 29) |	/* CLK_ON */ \
-					(1 << 28) |	/* CMD_MODE */ \
+					(0 << 28) |	/* CMD_MODE */ \
 					(4 << 25) |	/* DRAM_ROW_SELECT */ \
 					(3 << 21) |	/* DRAM_BANK_SELECT */ \
 					(0 << 18) |	/* SELF_REF_EN */ \
@@ -143,16 +146,12 @@
 					(0 <<  0) 	/* FIFO_UV_EN */ \
 				     )
 
-#define CONFIG_SYS_MDDRC_SYS_CFG_RUN	(CONFIG_SYS_MDDRC_SYS_CFG & ~(1 << 28))
+#define CONFIG_SYS_MDDRC_TIME_CFG0	0x030C3D2E
 #define CONFIG_SYS_MDDRC_TIME_CFG1	0x55D81189
 #define CONFIG_SYS_MDDRC_TIME_CFG2	0x34790863
 
-#define CONFIG_SYS_MDDRC_SYS_CFG_EN	0xF0000000
-#define CONFIG_SYS_MDDRC_TIME_CFG0	0x00003D2E
-#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN	0x030C3D2E
-
-#define CONFIG_SYS_MICRON_NOP		0x01380000
-#define CONFIG_SYS_MICRON_PCHG_ALL	0x01100400
+#define CONFIG_SYS_DDRCMD_NOP		0x01380000
+#define CONFIG_SYS_DDRCMD_PCHG_ALL	0x01100400
 #define CONFIG_SYS_MICRON_EMR	     (	(1 << 24) |	/* CMD_REQ */ \
 					(0 << 22) |	/* DRAM_CS */ \
 					(0 << 21) |	/* DRAM_RAS */ \
@@ -172,7 +171,7 @@
 				     )
 #define CONFIG_SYS_MICRON_EMR2		0x01020000
 #define CONFIG_SYS_MICRON_EMR3		0x01030000
-#define CONFIG_SYS_MICRON_RFSH		0x01080000
+#define CONFIG_SYS_DDRCMD_RFSH		0x01080000
 #define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
 #define CONFIG_SYS_MICRON_EMR_OCD    (	(1 << 24) |	/* CMD_REQ */ \
 					(0 << 22) |	/* DRAM_CS */ \
@@ -194,12 +193,12 @@
 
 /*
  * Backward compatible definitions,
- * so we do not have to change cpu/mpc512x/fixed_sdram.c
+ * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
  */
-#define	CONFIG_SYS_MICRON_EM2		(CONFIG_SYS_MICRON_EMR2)
-#define CONFIG_SYS_MICRON_EM3		(CONFIG_SYS_MICRON_EMR3)
-#define CONFIG_SYS_MICRON_EN_DLL	(CONFIG_SYS_MICRON_EMR)
-#define CONFIG_SYS_MICRON_OCD_DEFAULT	(CONFIG_SYS_MICRON_EMR_OCD)
+#define	CONFIG_SYS_DDRCMD_EM2		(CONFIG_SYS_MICRON_EMR2)
+#define CONFIG_SYS_DDRCMD_EM3		(CONFIG_SYS_MICRON_EMR3)
+#define CONFIG_SYS_DDRCMD_EN_DLL	(CONFIG_SYS_MICRON_EMR)
+#define CONFIG_SYS_DDRCMD_OCD_DEFAULT	(CONFIG_SYS_MICRON_EMR_OCD)
 
 /* DDR Priority Manager Configuration */
 #define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
@@ -245,7 +244,9 @@
  * NAND FLASH support
  * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
  */
-#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND					/* enable NAND support */
+#define CONFIG_JFFS2_NAND				/* with JFFS2 on it */
+
 
 #define CONFIG_NAND_MPC5121_NFC
 #define CONFIG_SYS_NAND_BASE		0x40000000
@@ -253,8 +254,6 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define NAND_MAX_CHIPS			CONFIG_SYS_MAX_NAND_DEVICE
 
-#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
-
 /*
  * Configuration parameters for MPC5121 NAND driver
  */
@@ -374,7 +373,6 @@
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
 #undef CONFIG_SOFT_I2C			/* so disable bit-banged I2C */
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 
 /* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SPEED		100000
@@ -433,6 +431,7 @@
 #undef CONFIG_CMD_FUSE
 #define CONFIG_CMD_I2C
 #undef CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
@@ -442,12 +441,38 @@
 #define CONFIG_CMD_PCI
 #endif
 
-#if defined(CONFIG_CMD_IDE)
+#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
 #define CONFIG_DOS_PARTITION
 #define CONFIG_MAC_PARTITION
 #define CONFIG_ISO_PARTITION
 #endif /* defined(CONFIG_CMD_IDE) */
 
+/*
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=f8000000.flash,nand0=mpc5121.nand"
+
+/*
+ * NOR flash layout:
+ *
+ * F8000000 - FEAFFFFF	107 MiB		User Data
+ * FEB00000 - FFAFFFFF	 16 MiB		Root File System
+ * FFB00000 - FFFEFFFF	  4 MiB		Linux Kernel
+ * FFF00000 - FFFBFFFF	768 KiB		U-Boot (up to 512 KiB) and 2 x * env
+ * FFFC0000 - FFFFFFFF	256 KiB		Device Tree
+ *
+ * NAND flash layout: one big partition
+ */
+#define MTDPARTS_DEFAULT	"mtdparts=f8000000.flash:107m(user),"	\
+						"16m(rootfs),"		\
+						"4m(kernel),"		\
+						"768k(u-boot),"		\
+						"256k(dtb);"		\
+					"mpc5121.nand:-(data)"
+
 /*
  * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
  * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE
@@ -541,9 +566,9 @@
 	"fdt_addr_r=880000\0"						\
 	"ramdisk_addr_r=900000\0"					\
 	"u-boot_addr=FFF00000\0"					\
-	"kernel_addr=FFC40000\0"					\
-	"fdt_addr=FFEC0000\0"						\
-	"ramdisk_addr=FC040000\0"					\
+	"kernel_addr=FFB00000\0"					\
+	"fdt_addr=FFFC0000\0"						\
+	"ramdisk_addr=FEB00000\0"					\
 	"ramdiskfile=aria/uRamdisk\0"				\
 	"u-boot=aria/u-boot.bin\0"					\
 	"fdtfile=aria/aria.dtb\0"					\