X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fatstk1006.h;h=bbe0aea8616f9e91c4ead982228c430ed476be56;hb=373a9788f05dfab47e01badc046459dead163104;hp=d681929a315f39eff6b1c6c1bf37df6c59be9431;hpb=09d623cdfdb0419cf98b45cf9c3d1279fbbf668f;p=u-boot

diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h
index d681929a31..bbe0aea861 100644
--- a/include/configs/atstk1006.h
+++ b/include/configs/atstk1006.h
@@ -3,42 +3,18 @@
  *
  * Configuration settings for the ATSTK1002 CPU daughterboard
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
 #include <asm/arch/hardware.h>
 
-#define CONFIG_AVR32
 #define CONFIG_AT32AP
 #define CONFIG_AT32AP7000
 #define CONFIG_ATSTK1006
 #define CONFIG_ATSTK1000
 
-#define CONFIG_ATSTK1000_EXT_FLASH
-
-/*
- * Timer clock frequency. We're using the CPU-internal COUNT register
- * for this, so this is equivalent to the CPU core clock frequency
- */
-#define CONFIG_SYS_HZ				1000
 
 /*
  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
@@ -122,7 +98,6 @@
  * "ethaddr" and "eth1addr". This is normally done during production.
  */
 #define CONFIG_OVERWRITE_ETHADDR_ONCE
-#define CONFIG_NET_MULTI
 
 /*
  * BOOTP options
@@ -154,18 +129,16 @@
 #define CONFIG_SYS_NR_PIOS			5
 #define CONFIG_SYS_HSDRAMC
 #define CONFIG_MMC
-#define CONFIG_ATMEL_MCI
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_GENERIC_MMC
 
 #define CONFIG_SYS_DCACHE_LINESZ		32
 #define CONFIG_SYS_ICACHE_LINESZ		32
 
 #define CONFIG_NR_DRAM_BANKS		1
 
-/* External flash on STK1000 */
-#if 0
-#define CONFIG_SYS_FLASH_CFI			1
-#define CONFIG_FLASH_CFI_DRIVER		1
-#endif
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
 
 #define CONFIG_SYS_FLASH_BASE			0x00000000
 #define CONFIG_SYS_FLASH_SIZE			0x800000
@@ -173,6 +146,7 @@
 #define CONFIG_SYS_MAX_FLASH_SECT		135
 
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_TEXT_BASE		0x00000000
 
 #define CONFIG_SYS_INTRAM_BASE			INTERNAL_SRAM_BASE
 #define CONFIG_SYS_INTRAM_SIZE			INTERNAL_SRAM_SIZE