X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fbf537-pnav.h;h=0913ce4e6916593e4d3286ea0c573cb3f79d6c5d;hb=374a235d42fa63cc84dbf384944a69b2d05bdc81;hp=c8a59ab57e7a029db858ca85944a6520758e03d2;hpb=f348ab85f741dc98b2d202c04b5f430eace94925;p=u-boot diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index c8a59ab57e..0913ce4e69 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -52,7 +52,7 @@ #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) @@ -85,7 +85,7 @@ */ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO @@ -94,7 +94,7 @@ * Env Storage Settings */ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_OFFSET 0x4000 #else @@ -105,6 +105,18 @@ #endif #define CONFIG_ENV_SIZE 0x1000 #define CONFIG_ENV_SECT_SIZE 0x2000 +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + arch/blackfin/lib/libblackfin.o (.text*); \ + arch/blackfin/cpu/libblackfin.o (.text*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text*); +#endif /* @@ -117,7 +129,6 @@ #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_READY PF12 #define BFIN_NAND_WRITE(addr, cmd) \ do { \ bfin_write8(addr, cmd); \ @@ -126,13 +137,7 @@ #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTHIO() & BFIN_NAND_READY) -#define NAND_PLAT_INIT() \ - do { \ - bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~BFIN_NAND_READY); \ - bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~BFIN_NAND_READY); \ - bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | BFIN_NAND_READY); \ - } while (0) +#define NAND_PLAT_GPIO_DEV_READY GPIO_PF12 /* @@ -140,8 +145,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /*