X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fcerf250.h;h=9696487907dd029b500de3b2c793448c3d64f20d;hb=7b89795f17c990263a17ecf25e447df16e379748;hp=71e5b58ddba7ea0f71e5fa45d1c4449fff096cd8;hpb=f61f1e150c84f5b9347fca79a4bc5f2286c545d2;p=u-boot

diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h
index 71e5b58ddb..9696487907 100644
--- a/include/configs/cerf250.h
+++ b/include/configs/cerf250.h
@@ -38,25 +38,30 @@
 #define CONFIG_CERF250		1	/* on Cerf PXA Board	    */
 #define BOARD_LATE_INIT		1
 #define CONFIG_BAUDRATE		38400
+#define	CONFIG_SYS_TEXT_BASE	0x0
 
 #undef	CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_NO_DCACHE
+
 /*
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
  */
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
 #define CONFIG_SMC91111_BASE 0x04000300
 #define CONFIG_SMC_USE_32_BIT
 
 /*
  * select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_FFUART	     1	/* we use FFUART on CERF PXA */
 
 /* allow to overwrite serial and ethaddr */
@@ -113,11 +118,9 @@
 #define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
 #define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
 
-#undef	CONFIG_SYS_CLKS_IN_HZ
-
 #define CONFIG_SYS_LOAD_ADDR		0xa2000000	/* default load address */
 
-#define CONFIG_SYS_HZ				3686400		/* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CPUSPEED		0x141		/* set core clock to 400/200/100 MHz */
 
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
@@ -137,15 +140,9 @@
 /*
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS	4			/* we have 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS		1		/* we have 1 bank of DRAM */
 #define PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE		0x04000000	/* 64 MB */
-#define PHYS_SDRAM_2			0xa4000000	/* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 MB */
-#define PHYS_SDRAM_3			0xa8000000	/* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE		0x00000000	/* 0 MB */
-#define PHYS_SDRAM_4			0xac000000	/* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE		0x00000000	/* 0 MB */
 
 #define PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
 #define PHYS_FLASH_2			0x04000000	/* Flash Bank #2 */
@@ -158,6 +155,9 @@
 
 #define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
 
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * GPIO settings
  */
@@ -181,6 +181,9 @@
 
 #define CONFIG_SYS_PSSR_VAL		0x20
 
+#define	CONFIG_SYS_CCCR			CCCR_L27|CCCR_M2|CCCR_N10
+#define	CONFIG_SYS_CKEN			0x0
+
 /*
  * Memory settings
  */
@@ -190,6 +193,8 @@
 #define CONFIG_SYS_MDCNFG_VAL		0x00001AC9
 #define CONFIG_SYS_MDREFR_VAL		0x03CDC017
 #define CONFIG_SYS_MDMRS_VAL		0x00000000
+#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
 
 /*
  * PCMCIA and CF Interfaces