X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fcgtqmx6eval.h;h=03b17840e57fd2ebc5f26c70271a5e9df4a3dd98;hb=84035fccbe54af1d0513e6288e08a45885ee872c;hp=63e3b94bb55975d5094aef196b7f75e0eea20b17;hpb=814013253fd4cf932d0fb32f7043f09a2a748d9a;p=u-boot diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 63e3b94bb5..03b17840e5 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * * Congatec Conga-QEVAl board configuration file. @@ -6,8 +7,6 @@ * Based on Freescale i.MX6Q Sabre Lite board configuration file. * Copyright (C) 2013, Adeneo Embedded * Leo Sartre, - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_CGTQMX6EVAL_H @@ -18,20 +17,13 @@ #define CONFIG_MACH_TYPE 4122 #ifdef CONFIG_SPL -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_SPI_SUPPORT -#define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) -#define CONFIG_SPL_SPI_LOAD #include "imx6_spl.h" #endif /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT #define CONFIG_MISC_INIT_R #define CONFIG_MXC_UART @@ -41,23 +33,17 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 /* SPI NOR */ -#define CONFIG_CMD_SF #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_SST -#define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) -/* Miscellaneous commands */ -#define CONFIG_CMD_BMODE - /* Thermal support */ #define CONFIG_IMX_THERMAL /* I2C Configs */ -#define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ @@ -72,95 +58,45 @@ #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* USB Configs */ -#define CONFIG_CMD_USB -#define CONFIG_CMD_FAT -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 -#define CONFIG_USB_STORAGE #define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ -#define CONFIG_USB_KEYBOARD -#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP -#define CONFIG_CI_UDC #define CONFIG_USBD_HS -#define CONFIG_USB_GADGET_DUALSPEED - -#define CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USB_FUNCTION_MASS_STORAGE -#define CONFIG_USB_GADGET_DOWNLOAD -#define CONFIG_USB_GADGET_VBUS_DRAW 2 - -#define CONFIG_G_DNL_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 -#define CONFIG_G_DNL_MANUFACTURER "Congatec" - -/* USB Device Firmware Update support */ -#define CONFIG_CMD_DFU -#define CONFIG_USB_FUNCTION_DFU -#define CONFIG_DFU_MMC -#define CONFIG_DFU_SF - -#define CONFIG_USB_FUNCTION_FASTBOOT -#define CONFIG_CMD_FASTBOOT -#define CONFIG_ANDROID_BOOT_IMAGE -#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 /* Framebuffer */ -#define CONFIG_VIDEO #define CONFIG_VIDEO_IPUV3 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN #define CONFIG_BMP_16BPP #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO -#ifdef CONFIG_MX6DL -#define CONFIG_IPUV3_CLK 198000000 -#else -#define CONFIG_IPUV3_CLK 264000000 -#endif #define CONFIG_IMX_HDMI /* SATA */ -#define CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 -#define CONFIG_LIBATA /* Ethernet */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII #define CONFIG_FEC_MXC #define CONFIG_MII #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 6 -#define CONFIG_PHYLIB #define CONFIG_PHY_ATHEROS /* Command definition */ #define CONFIG_MXC_UART_BASE UART2_BASE -#define CONFIG_CONSOLE_DEV "ttymxc1" +#define CONSOLE_DEV "ttymxc1" #define CONFIG_MMCROOT "/dev/mmcblk0p2" #define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ @@ -168,7 +104,7 @@ "fdt_addr_r=0x18000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "console=" CONFIG_CONSOLE_DEV "\0" \ + "console=" CONSOLE_DEV "\0" \ "dfuspi=dfu 0 sf 0:0:10000000:0\0" \ "dfu_alt_info_spl=spl raw 0x400\0" \ "dfu_alt_info_img=u-boot raw 0x10000\0" \ @@ -268,7 +204,6 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR @@ -287,7 +222,6 @@ #define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_IS_IN_SPI_FLASH #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) #define CONFIG_ENV_OFFSET (768 * 1024) #define CONFIG_ENV_SECT_SIZE (64 * 1024)