X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fcm_t335.h;h=bd41a566411c7ecd599a4768f38cf82f0aebdd02;hb=27fbdcdefd87411e12c1d1caac1019d2b37a9eb7;hp=9a8e1302c56034881a068257d44391a0796e9457;hpb=5c84ad097d829bb1e6460438f33e1536b23b3c9b;p=u-boot

diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
index 9a8e1302c5..bd41a56641 100644
--- a/include/configs/cm_t335.h
+++ b/include/configs/cm_t335.h
@@ -12,13 +12,10 @@
 #define __CONFIG_CM_T335_H
 
 #define CONFIG_CM_T335
-#define CONFIG_NAND
 
 #include <configs/ti_am335x_common.h>
 
 #undef CONFIG_SPI
-#undef CONFIG_OMAP3_SPI
-#undef CONFIG_BOOTCOUNT_LIMIT
 #undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
 
 #undef CONFIG_MAX_RAM_BANK_SIZE
@@ -45,8 +42,8 @@
 		"bootm ${loadaddr}\0"
 
 #define NANDARGS \
-	"mtdids=" MTDIDS_DEFAULT "\0" \
-	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
 	"nandroot=ubi0:rootfs rw\0" \
 	"nandrootfstype=ubifs\0" \
 	"nandargs=setenv bootargs console=${console} " \
@@ -99,11 +96,8 @@
 #define CONFIG_SYS_I2C_EEPROM_BUS	0
 
 /* SPL */
-#define CONFIG_SPL_LDSCRIPT		"arch/arm/mach-omap2/u-boot-spl.lds"
 
 /* Network. */
-#define CONFIG_PHY_GIGE
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
 /* NAND support */
@@ -130,20 +124,11 @@
 #undef CONFIG_SYS_NAND_U_BOOT_OFFS
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x200000
 
-#define CONFIG_CMD_NAND
-#define MTDIDS_DEFAULT			"nand0=nand"
-#define MTDPARTS_DEFAULT		"mtdparts=nand:2m(spl)," \
-					"1m(u-boot),1m(u-boot-env)," \
-					"1m(dtb),4m(splash)," \
-					"6m(kernel),-(rootfs)"
-#define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_OFFSET		0x300000 /* environment starts here */
 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 #ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_CMD_SPL_NAND_OFS		0x400000 /* un-assigned: (using dtb) */
 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x500000
-#define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
 #endif
 
 /* GPIO pin + bank to pin ID mapping */
@@ -153,24 +138,18 @@
 /* Status LED polarity is inversed, so init it in the "off" state */
 
 /* EEPROM */
-#define CONFIG_CMD_EEPROM
 #define CONFIG_ENV_EEPROM_IS_ON_I2C
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
 #define CONFIG_SYS_EEPROM_SIZE			256
 
-#define CONFIG_CMD_EEPROM_LAYOUT
-#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
-
 #ifndef CONFIG_SPL_BUILD
 /*
  * Enable PCA9555 at I2C0-0x26.
  * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command.
  */
 #define CONFIG_PCA953X
-#define CONFIG_CMD_PCA953X
-#define CONFIG_CMD_PCA953X_INFO
 #define CONFIG_SYS_I2C_PCA953X_ADDR	0x26
 #define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x26, 16} }
 #endif /* CONFIG_SPL_BUILD */