X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fcoreboot.h;h=2fefdc80db68e7ea5b72d6493c32ef8add701c44;hb=f9c1456cf632175afb7d6b27f42f1aab8432be0f;hp=a4aa8f74535e4d3f1d769e8b2c4e51759c2a840a;hpb=fed029f3c31b7d5df674b5090a13356b631918c7;p=u-boot diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index a4aa8f7453..2fefdc80db 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -38,9 +38,9 @@ #define CONFIG_SHOW_BOOT_PROGRESS #define CONFIG_LAST_STAGE_INIT #define CONFIG_SYS_VSNPRINTF -#define CONFIG_INTEL_CORE_ARCH /* Sandy bridge and ivy bridge chipsets. */ #define CONFIG_ZBOOT_32 #define CONFIG_PHYSMEM +#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_LMB #define CONFIG_OF_LIBFDT @@ -48,6 +48,19 @@ #define CONFIG_OF_SEPARATE #define CONFIG_DEFAULT_DEVICE_TREE link +#define CONFIG_BOOTSTAGE +#define CONFIG_BOOTSTAGE_REPORT +#define CONFIG_BOOTSTAGE_FDT +#define CONFIG_CMD_BOOTSTAGE +/* Place to stash bootstage data from first-stage U-Boot */ +#define CONFIG_BOOTSTAGE_STASH 0x0110f000 +#define CONFIG_BOOTSTAGE_STASH_SIZE 0x7fc +#define CONFIG_BOOTSTAGE_USER_COUNT 60 + +#define CONFIG_LZO +#undef CONFIG_ZLIB +#undef CONFIG_GZIP + /*----------------------------------------------------------------------- * Watchdog Configuration */ @@ -77,7 +90,8 @@ #endif /* Generic TPM interfaced through LPC bus */ -#define CONFIG_GENERIC_LPC_TPM +#define CONFIG_TPM +#define CONFIG_TPM_TIS_LPC #define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 /*----------------------------------------------------------------------- @@ -217,7 +231,6 @@ #define CONFIG_SYS_MEMTEST_END 0x01000000 #define CONFIG_SYS_LOAD_ADDR 0x100000 #define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_X86_ISR_TIMER /*----------------------------------------------------------------------- * SDRAM Configuration @@ -234,8 +247,9 @@ * CPU Features */ -#define CONFIG_SYS_GENERIC_TIMER +#define CONFIG_SYS_X86_TSC_TIMER #define CONFIG_SYS_PCAT_INTERRUPTS +#define CONFIG_SYS_PCAT_TIMER #define CONFIG_SYS_NUM_IRQS 16 /*-----------------------------------------------------------------------