X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fcorenet_ds.h;h=4e2b3fb983d53ce35106bb9d1f993c33594f8174;hb=30f3413ef2629ede59e63e0a84f69a70748c09a6;hp=2733fb21e353c2f24268586bf3ada0d3bdcd612a;hpb=f2b382ea066d02d5ba44870024cc1295e85782ef;p=u-boot diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 2733fb21e3..4e2b3fb983 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -28,6 +28,11 @@ #include "../board/freescale/common/ics307_clk.h" +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ @@ -37,6 +42,14 @@ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MP /* support multiple processors */ +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ @@ -46,8 +59,8 @@ #define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_SYS_HAS_SERDES /* has SERDES */ +#define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ @@ -55,16 +68,20 @@ #define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_RAMBOOT_PBL) + #define CONFIG_SYS_NO_FLASH /* Store ENV in memory only */ +#endif + #ifdef CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_NOWHERE #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ -#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ /* * These can be toggled for performance analysis, otherwise use default. @@ -73,7 +90,7 @@ #define CONFIG_BACKSIDE_L2_CACHE #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #define CONFIG_BTB /* toggle branch predition */ -/*#define CONFIG_DDR_ECC*/ +#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef @@ -92,6 +109,18 @@ #define CONFIG_SYS_ALT_MEMTEST #define CONFIG_PANIC_HANG /* do not reset board on panic */ +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) +#else +#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR +#endif +#define CONFIG_SYS_L3_SIZE (1024 << 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) + /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) @@ -185,6 +214,10 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} @@ -211,10 +244,9 @@ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS #endif -#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (512 * 1024) @@ -264,21 +296,21 @@ /* * RapidIO */ -#define CONFIG_SYS_RIO1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_RIO1_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_RIO1_MEM_PHYS 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_RIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_RIO2_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_RIO2_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull #else -#define CONFIG_SYS_RIO2_MEM_PHYS 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 #endif -#define CONFIG_SYS_RIO2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ /* * General PCI @@ -351,6 +383,7 @@ #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ /* Qman/Bman */ +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 #ifdef CONFIG_PHYS_64BIT @@ -383,33 +416,10 @@ #endif #ifdef CONFIG_PCI - -/*PCIE video card used*/ -#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT - -/* video */ -#define CONFIG_VIDEO - -#ifdef CONFIG_VIDEO -#define CONFIG_BIOSEMU -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_ATI_RADEON_FB -#define CONFIG_VIDEO_LOGO -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET -#endif - #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_E1000 -#ifndef CONFIG_PCI_PNP -#define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS -#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS -#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ -#endif - #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION #endif /* CONFIG_PCI */ @@ -440,13 +450,11 @@ #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 -#if (CONFIG_SYS_NUM_FMAN == 2) #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 -#endif #define CONFIG_SYS_TBIPA_VALUE 8 #define CONFIG_MII /* MII PHY management */ @@ -457,7 +465,6 @@ /* * Environment */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ @@ -476,6 +483,7 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_DHCP #ifdef CONFIG_PCI #define CONFIG_CMD_PCI @@ -529,6 +537,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */